公开(公告)号：US11804426B2

公开(公告)日：2023-10-31

申请号：US17379724

申请日：2021-07-19

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/181 ,  H05K7/023

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US11721632B2

公开(公告)日：2023-08-08

申请号：US16665644

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/351

Abstract: Embodiments include a package substrate, a semiconductor package, and a method of forming the package substrate. A package substrate includes a core substrate between a first alternate core substrate and a second alternate core substrate. The first alternate core substrate includes conductive layers and vias. The package substrate includes a dielectric layer surrounding the core and first and second alternate substrates, a first conductive layer on a top surface of the dielectric layer, and a second conductive layer on top surfaces of the core and first and second alternate substrates, where the dielectric layer is over/under the core and first and second alternate substrates. The package substrate includes a third conductive layer on bottom surfaces of the core and first and second alternate substrates. The conductive layers are coupled to the vias within the first alternate core substrate, where the conductive layers and vias couple the second and third layers.

公开(公告)号：US20230223278A1

公开(公告)日：2023-07-13

申请号：US18118835

申请日：2023-03-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Shuckman

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20220293327A1

公开(公告)日：2022-09-15

申请号：US17199005

申请日：2021-03-11

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Sri Chaitra Jyotsna Chavali ,  Robert L. Sankman ,  Anne Augustine ,  Kaladhar Radhakrishnan

IPC: H01F27/26 ,  H01F27/40 ,  H01F41/04

Abstract: An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

公开(公告)号：US20210242132A1

公开(公告)日：2021-08-05

申请号：US17234997

申请日：2021-04-20

Applicant: INTEL CORPORATION

Inventor： Sri Chaitra Jyotsna Chavali

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/00

Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

公开(公告)号：US10980129B2

公开(公告)日：2021-04-13

申请号：US16819899

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Amruthavalli Pallavi Alur ,  Wei-Lun Kane Jen ,  Sriram Srinivasan

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/30 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

公开(公告)号：US12261124B2

公开(公告)日：2025-03-25

申请号：US16724907

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/498

Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20230162902A1

公开(公告)日：2023-05-25

申请号：US17531954

申请日：2021-11-22

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Kyu Oh Lee ,  Sri Chaitra Jyotsna Chavali ,  Vijaya Boddu ,  Krishna Bharath ,  Robert L. Sankman

IPC: H01F27/02 ,  H01F41/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01F27/022 ,  H01F41/0206 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/4857 ,  H01L21/486

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a package with integrated inductors. In selected examples, the package includes a core layer having a core thickness and through holes. The package further includes inductor structures within the through holes, such that an inductor structure has a length exceeding the core thickness.

公开(公告)号：US11631595B2

公开(公告)日：2023-04-18

申请号：US17521406

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.