公开(公告)号：US06941957B2

公开(公告)日：2005-09-13

申请号：US10621252

申请日：2003-07-16

申请人： Kuo-Feng Chen ,  Hsiu-Mei Yu ,  Charles Tseng ,  Ta-Yang Lin

发明人： Kuo-Feng Chen ,  Hsiu-Mei Yu ,  Charles Tseng ,  Ta-Yang Lin

IPC分类号： H01L21/288 ,  H01L21/60 ,  H01L23/485 ,  B08B3/02

CPC分类号： H01L21/2885 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S134/902 ,  H01L2924/00

摘要： A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.

摘要翻译： 一种方法，包括提供具有接触焊盘的衬底和覆盖接触焊盘的下凸块冶金的步骤，以及覆盖凸块下金属的光致抗蚀剂层，并且其中光致抗蚀剂层具有限定在其下的凸起到下凸块冶金 并与接触垫对准。 在第一种润湿溶液镀覆第一种子层之前，先在底部凸起冶金上预处理基材。 此后，将第一种子层的电镀被镀在凸块下的金属上。

公开(公告)号：US06624060B2

公开(公告)日：2003-09-23

申请号：US10045782

申请日：2002-01-12

申请人： Kuo-Feng Chen ,  Hsiu-Mei Yu ,  Charles Tseng ,  Ta-Yang Lin

发明人： Kuo-Feng Chen ,  Hsiu-Mei Yu ,  Charles Tseng ,  Ta-Yang Lin

IPC分类号： H01L2144

CPC分类号： H01L21/2885 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S134/902 ,  H01L2924/00

摘要： A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.

摘要翻译： 一种方法，包括提供具有接触焊盘的衬底和覆盖接触焊盘的下凸块冶金的步骤，以及覆盖凸块下金属的光致抗蚀剂层，并且其中光致抗蚀剂层具有限定在其下的凸起到下凸块冶金 并与接触垫对准。 在第一种润湿溶液镀覆第一种子层之前，先在底部凸起冶金上预处理基材。 此后，将第一种子层的电镀被镀在凸块下的金属上。

公开(公告)号：US06696356B2

公开(公告)日：2004-02-24

申请号：US10038847

申请日：2001-12-31

申请人： Li-Hsin Tseng ,  Hsiu-Mei Yu ,  Ta-Yang Lin ,  Fang-Chung Liu ,  Kai-Ming Ching ,  Tung-Heng Shie

发明人： Li-Hsin Tseng ,  Hsiu-Mei Yu ,  Ta-Yang Lin ,  Fang-Chung Liu ,  Kai-Ming Ching ,  Tung-Heng Shie

IPC分类号： H01L2144

CPC分类号： H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014

摘要： A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad. Thereafter the remaining portions of the photoresist layer are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

摘要翻译： 在半导体晶片或倒装芯片等基板上形成凸块而不产生金属带残留物的方法。 该方法包括提供具有接触焊盘并具有上钝化层和形成在上钝化层中的开口的半导体器件的步骤，暴露接触焊盘的一部分。 在上钝化层和接触焊盘上沉积凸块下冶金。 光致抗蚀剂层沉积在凸块下的金属上。 光致抗蚀剂层是干膜光致抗蚀剂。 光致抗蚀剂层被图案化以在光致抗蚀剂层中提供直到下凸块冶金并且与接触垫对准的开口。 对光致抗蚀剂层施加额外的能量以提高光致抗蚀剂层对凸块下金属的粘合性。 将导电材料沉积在形成在光致抗蚀剂层中的开口中，并且覆盖凸块下方的金属并与接触焊盘对准。 此后，除去光致抗蚀剂层的其余部分。 导电材料被重熔以在半导体器件上提供凸块。

公开(公告)号：US06486054B1

公开(公告)日：2002-11-26

申请号：US10058472

申请日：2002-01-28

申请人： Yang-Tung Fan ,  Hsiu-Mei Yu ,  Li-Hsin Tseng ,  Kuang-Peng Lin ,  Ta-Yang Lin

发明人： Yang-Tung Fan ,  Hsiu-Mei Yu ,  Li-Hsin Tseng ,  Kuang-Peng Lin ,  Ta-Yang Lin

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00014

摘要： The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.

摘要翻译： 本发明教导了如何在不需要牺牲面密度的情况下实现更大的焊球高度。 形成焊料的模具分两步制成。 在第一次曝光中，对负光致抗蚀剂（优选DFR）进行图案化以形成传统的圆柱形模具。 然而，曝光和显影时间被调整为使得厚度减小的未曝光和未显影的抗蚀剂层覆盖在模具的地板上。 该残余抗蚀剂层被给予第二曝光，并且在显影之后在第一模具的底部形成环形插入件。 在模具已经填充有焊料（通过电镀或通过使用焊膏）之后，它被去除，结果是由两个相邻的同轴圆柱体构成的焊料凸块，其中上部具有较大的直径。 重熔后，具有这种形状的凸起形成扁球体而不是球体。

公开(公告)号：US20060113640A1

公开(公告)日：2006-06-01

申请号：US10998423

申请日：2004-11-29

申请人： Hsiu-Mei Yu ,  Ken-Shen Chou ,  Shun-Liang Hsu

发明人： Hsiu-Mei Yu ,  Ken-Shen Chou ,  Shun-Liang Hsu

IPC分类号： H01L23/58

CPC分类号： H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

摘要： In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.

摘要翻译： 在一个实施方案中，本公开涉及通过注入表面回收聚合物绝缘层的方法和装置。 该方法包括提供其上具有导电焊盘和绝缘层的衬底，任选地处理导电焊盘以去除形成在导电焊盘上的氧化物层并导电离子注入以恢复绝缘层的介电性能。

公开(公告)号：US08624392B2

公开(公告)日：2014-01-07

申请号：US13152734

申请日：2011-06-03

申请人： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

发明人： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L21/76885 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/82 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10155 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/207 ,  H01L2924/2076 ,  H01L2224/05552

摘要： A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

摘要翻译： 提供了一种用于提供后钝化和欠掺杂金属化的系统和方法。 一个实施例包括大于上覆下凸点金属化的后钝化层。 延伸超过下凸块金属化的后钝化层屏蔽下层不受材料的热膨胀系数的不匹配产生的应力。

公开(公告)号：US20110241179A1

公开(公告)日：2011-10-06

申请号：US13164523

申请日：2011-06-20

申请人： Ming-Chang Hsieh ,  Hung-Lin Chen ,  Hsiu-Mei Yu ,  Chin Kun Lan ,  Dong-Lung Lee

发明人： Ming-Chang Hsieh ,  Hung-Lin Chen ,  Hsiu-Mei Yu ,  Chin Kun Lan ,  Dong-Lung Lee

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

摘要翻译： 本公开提供了一种制造集成电路（IC）装置的方法。 该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

公开(公告)号：US07968431B2

公开(公告)日：2011-06-28

申请号：US12173121

申请日：2008-07-15

申请人： Ming-Chang Hsieh ,  Hung-Lin Chen ,  Hsiu-Mei Yu ,  Chin Kun Lan ,  Dong-Lung Lee

发明人： Ming-Chang Hsieh ,  Hung-Lin Chen ,  Hsiu-Mei Yu ,  Chin Kun Lan ,  Dong-Lung Lee

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

摘要翻译： 本公开提供了一种制造集成电路（IC）装置的方法。 该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

公开(公告)号：US20080303154A1

公开(公告)日：2008-12-11

申请号：US11811660

申请日：2007-06-11

申请人： Hon-Lin Huang ,  Boe Su ,  Li-Hsin Tseng ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

发明人： Hon-Lin Huang ,  Boe Su ,  Li-Hsin Tseng ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

IPC分类号： H01L23/528 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/05 ,  H01L2221/6834 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask.

摘要翻译： 提供一种集成电路结构及其形成方法。 该方法包括提供基板; 形成延伸到衬底中的穿硅通孔（TSV）开口; 在TSV开口中形成凸块下冶金（UBM），其中UBM延伸出TSV开口; 用金属材料填充TSV开口; 在所述金属材料上形成图案化的盖层; 并且将所述UBM的一部分蚀刻在所述TSV开口外部，其中所述图案化盖层用作掩模。

公开(公告)号：US07378724B2

公开(公告)日：2008-05-27

申请号：US11166454

申请日：2005-06-24

申请人： Hsiu-Mei Yu ,  Gil Huang ,  Chien-Tung Yu ,  Owen Chen

发明人： Hsiu-Mei Yu ,  Gil Huang ,  Chien-Tung Yu ,  Owen Chen

IPC分类号： H01L23/02

CPC分类号： H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.

摘要翻译： 提供了一种在半导体器件上提供空腔结构的方法。 在封装图像传感器中特别有用的形成腔结构的方法包括在衬底上形成间隔层。 间隔层可以由感光材料形成，光敏材料可以使用光刻技术进行图案化以在晶片上形成周围的模具的空腔壁。 包装层，例如基本上透明的层，可以在固化之前直接放置在空腔壁上。 在另一个实施例中，空腔壁被固化，将粘合剂施加到空腔壁的表面，并且将包装层放置在粘合剂上。 此后，可以对晶片进行切割，并且可以将各个管芯封装使用。