公开(公告)号：US10932358B2

公开(公告)日：2021-02-23

申请号：US16114669

申请日：2018-08-28

Applicant: MEDIATEK INC.

Inventor： Duen-Yi Ho ,  Hung-Chuan Chen ,  Shang-Pin Chen

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  G06F13/40 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

公开(公告)号：US20180322914A1

公开(公告)日：2018-11-08

申请号：US15959303

申请日：2018-04-23

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Shang-Pin Chen

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096

Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.

公开(公告)号：US10109341B2

公开(公告)日：2018-10-23

申请号：US15298262

申请日：2016-10-20

Applicant: MEDIATEK Inc.

Inventor： Bo-Wei Hsieh ,  Shang-Pin Chen

IPC: G11C7/00 ,  G11C11/4074 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4072

Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.

公开(公告)号：US09859900B2

公开(公告)日：2018-01-02

申请号：US15091588

申请日：2016-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Sheng-Feng Lee

IPC: H03L1/00 ,  G01R31/317 ,  H03L7/00 ,  H04L7/00 ,  H04L7/06

CPC classification number: H03L1/00 ,  G01R31/31709 ,  H03L7/00 ,  H04L7/0087 ,  H04L7/065

Abstract: A jitter control circuit within a chip comprises an adaptive PDN, a current generator and a jitter generator. The adaptive PDN is capable of being controlled/modulated to provide difference impedances. The current generator is coupled to the adaptive PDN, and is arranged for receiving a supply voltage provided by the adaptive PDN and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN, and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN.

公开(公告)号：US09825627B2

公开(公告)日：2017-11-21

申请号：US15183804

申请日：2016-06-16

Applicant: MEDIATEK INC.

Inventor： An-Siou Li ,  Shang-Pin Chen

IPC: H03K3/00 ,  H03K17/687 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/04

CPC classification number: H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: An apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.

公开(公告)号：US09871518B2

公开(公告)日：2018-01-16

申请号：US15247903

申请日：2016-08-25

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Chia-Yu Chan ,  Bo-Wei Hsieh

IPC: H03K19/00 ,  G11C5/00 ,  G11C7/10 ,  G11C11/4074 ,  G06F3/06 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G11C5/04

CPC classification number: H03K19/0005 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

公开(公告)号：US20170345480A1

公开(公告)日：2017-11-30

申请号：US15480382

申请日：2017-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/022 ,  Y02D10/14

Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.

公开(公告)号：US09824728B2

公开(公告)日：2017-11-21

申请号：US14294094

申请日：2014-06-02

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: H03K17/16 ,  G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  H03K19/0185 ,  H04L25/02 ,  G06F13/16

CPC classification number: G11C7/109 ,  G06F13/1689 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298

Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

公开(公告)号：US20170133078A1

公开(公告)日：2017-05-11

申请号：US15298262

申请日：2016-10-20

Applicant: MEDIATEK Inc.

Inventor： Bo-Wei Hsieh ,  Shang-Pin Chen

IPC: G11C11/4074 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2211/4067

Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.

公开(公告)号：US09613665B2

公开(公告)日：2017-04-04

申请号：US14535299

申请日：2014-11-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C7/10 ,  G06F1/10 ,  G06F1/08 ,  G06F1/04 ,  G11C7/22 ,  H03L7/081 ,  H03L7/099

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0994 ,  H03L2207/50

Abstract: A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift.