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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06646350B2

    公开(公告)日：2003-11-11

    申请号：US09922230

    申请日：2001-08-03

    申请人： Naotaka Tanaka ,  Hideo Miura ,  Yoshiyuki Kado ,  Ikuo Yoshida ,  Takahiro Naito

    发明人： Naotaka Tanaka ,  Hideo Miura ,  Yoshiyuki Kado ,  Ikuo Yoshida ,  Takahiro Naito

    IPC分类号： H01L2352

    CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/00

    摘要： In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C. By setting or selecting the physical properties in the manner disclosed above, it is possible to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric bonding between the bump pads (2) formed on the LSI chips (1) and the electrode pads (4) on the interconnection substrate (5) within an guaranteed temperature range.

    摘要翻译： 为了实现能够保持高可靠性的半导体器件及其制造方法，在形成在LSI芯片上的每个凸块焊盘和形成在互连基板上的每个电极焊盘之间的电连接在保证的温度范围内， 粘合剂（3）的膨胀系数在20〜60ppm的范围内，积聚部（6）的弹性模量在5〜10GPa的范围内。 此外，积存部（6）由多层积层基板构成，在该多层积层基板中，增益部分的损耗系数的峰值（玻璃化转变温度）存在于100℃〜 250℃，并且不存在于0℃至100℃的范围内。通过以上述方式设置或选择物理性质，可以实现可以保持的半导体器件及其制造方法 在保证温度范围内，形成在LSI芯片（1）上的凸块焊盘（2）和互连基板（5）上的电极焊盘（4）之间的电连接具有高可靠性。

    Semiconductor device and method of manufacturing the same
    5.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07241685B2

    公开(公告)日：2007-07-10

    申请号：US10390413

    申请日：2003-03-18

    申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

    发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

    IPC分类号： H01L21/44

    CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

    摘要翻译： 提供一种具有降低短路可能性的布线结构的半导体器件及其制造方法。 此外，提供了具有高可靠性的半导体器件。 此外，提供了一种具有高产率的半导体器件。 在半导体衬底的一个主表面侧形成布线，并且具有相邻导体层和主布线层的叠层结构。 主配线层包含一个添加的元素以防止迁移。 相邻的导体层由用于防止主要构成元素和主配线层的添加元素扩散到相邻导体层下方的基板中的材料形成，并且添加元素在靠近界面处的位置的浓度 与相邻的导体层间隔开的主配线层的添加元素的浓度相比，相邻的导体层和主布线层的电位低。

    Optical device having connections with optical members through protective medium
    6.
    发明申请
    Optical device having connections with optical members through protective medium 有权
    光学装置通过保护介质与光学构件连接

    公开(公告)号：US20070140617A1

    公开(公告)日：2007-06-21

    申请号：US11591560

    申请日：2006-11-02

    申请人： Shinichi Shimotsu ,  Shinichiro Sonoda ,  Hideo Miura

    发明人： Shinichi Shimotsu ,  Shinichiro Sonoda ,  Hideo Miura

    IPC分类号： G02B6/32 ,  G02B6/26 ,  G02B6/42

    CPC分类号： G02B6/262 ,  G02B6/32 ,  G02B6/421

    摘要： An optical device includes: a first optical member having a light-exit end at which light exits the first optical member; a second optical member having a light-entrance end which abuts the light-exit end through a protective medium and from which the light enters the second optical member; and the protective medium which is arranged between the light-exit end and the light-entrance end, and suppresses fixing together of the light-exit end and the light-entrance end. Specifically, the protective medium is transparent and arranged between the light-exit end and the light-entrance end, and is reusable even after the light-exit end and the light-entrance end are pressed together with a pressure of approximately 0.5 or 1 kgf and are then separated from each other.

    摘要翻译： 光学装置包括：具有光出射端的第一光学构件，光从该第一光学构件出射; 第二光学构件，其具有通过保护介质邻接所述光出射端的光入射端，并且所述光进入所述第二光学构件; 以及布置在光出射端和光入射端之间的保护介质，并且抑制光出射端和光入射端的固定在一起。 具体地说，保护介质是透明的并且设置在光出射端和光入射端之间，并且即使在光出射端和光入射端之间也以约0.5或1kgf的压力被压在一起 然后彼此分离。

    Miniaturized semiconductor device with improved dielectric properties
    7.
    发明授权
    Miniaturized semiconductor device with improved dielectric properties 有权
    具有改善介电特性的小型半导体器件

    公开(公告)号：US07217971B2

    公开(公告)日：2007-05-15

    申请号：US10848473

    申请日：2004-05-17

    申请人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    IPC分类号： H01L31/119

    CPC分类号： H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

    摘要： Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

    摘要翻译： 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅介质膜6,7的主要成分。 栅介质膜6,7例如通过CVD形成。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。 在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气 扩散被控制。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

    Method of designing a semiconductor device
    10.
    发明授权
    Method of designing a semiconductor device 失效
    设计半导体器件的方法

    公开(公告)号：US06949387B2

    公开(公告)日：2005-09-27

    申请号：US10626718

    申请日：2003-07-25

    申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

    IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L21/66

    CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

    摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

    摘要翻译： 提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至 还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度 的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值 发生脱位。