公开(公告)号：US4970571A

公开(公告)日：1990-11-13

申请号：US248101

申请日：1988-09-23

Applicant: Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

Inventor： Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1358 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014

Abstract: According to the present invention, there is provided a method for forming a bump and comprising the steps of dipping a semiconductor element with an Al electrode and a passivation film formed thereon in a palladium solution containing 5 to 2,000 ppm of at least one element selected from the group consisting of Zn, Pb, Sn, Cd, and Cr, selectively precipitating palladium on the electrode, and conducting electroless nickel-plating on the semiconductor element, including the electrode on which palladium is precipitated.

公开(公告)号：US4797530A

公开(公告)日：1989-01-10

申请号：US939969

申请日：1986-12-10

Applicant: Nobuo Iwase

Inventor： Nobuo Iwase

IPC: H01L23/12 ,  C04B41/00 ,  C04B41/53 ,  C04B41/80 ,  C04B41/91 ,  H05K3/10 ,  B23K26/00

CPC classification number: C04B41/009 ,  C04B41/0036 ,  C04B41/53 ,  C04B41/80 ,  C04B41/91 ,  H05K3/105 ,  C04B2111/00844 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49171 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49155

Abstract: A ceramic circuit substrate can be manufactured by a method comprising the steps of (i) providing an electrically insulating ceramic substrate; and (ii) irradiating a predetermined region of said ceramic substrate with an energy beam such that at least a portion of said region is rendered conductive.

Abstract translation: 陶瓷电路基板可以通过包括以下步骤的方法制造：（i）提供电绝缘陶瓷基板; 和（ii）用能量束照射所述陶瓷衬底的预定区域，使得所述区域的至少一部分变得导电。

公开(公告)号：US4659611A

公开(公告)日：1987-04-21

申请号：US706280

申请日：1985-02-27

Applicant: Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

Inventor： Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

IPC: C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  C04B35/52 ,  B32B5/16 ,  B32B15/04 ,  C04B35/58

CPC classification number: C04B41/009 ,  C04B41/5111 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/3731 ,  C04B2111/00844 ,  H01L2924/0002 ,  H05K1/0306 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A high thermal conductivity circuit substrate is provided comprising a sintered aluminum nitride ceramic substrate consisting essentially of one member selected from the group of yttrium, the rare earth metals and the alkali earth metals and an electrically conductive thick film paste for a conductive layer formed on the substrate.

Abstract translation: 提供了一种高导热性电路基板，其包括基本上由选自钇，稀土金属和碱土金属的一种元素组成的烧结氮化铝陶瓷基板，以及形成在导电层上的导电厚膜糊 基质。

公开(公告)号：US5453991A

公开(公告)日：1995-09-26

申请号：US31730

申请日：1993-03-15

Applicant: Kouhei Suzuki ,  Kouji Suzuki ,  Miki Mori ,  Akinori Hongu ,  Nobuo Iwase

Inventor： Kouhei Suzuki ,  Kouji Suzuki ,  Miki Mori ,  Akinori Hongu ,  Nobuo Iwase

IPC: G06F11/273 ,  G06F7/02

CPC classification number: G06F11/2733

Abstract: A highly-integrated semiconductor IC device includes a semiconductive substrate, on which an internal function circuit is arranged to have a first plurality of input terminals and a second plurality of output terminals. A logic circuit is arranged on the substrate and is connected to the internal circuit through the output terminals. The logic circuit has a third plurality of output terminals, which are less in number than the outputs of the internal circuit. These logic output terminals are coupled to the same number of inspection terminals, which are adapted to be coupled to a known electric inspection tool. The logic circuit processes the voltage signals appearing at the output terminals of the internal circuit so as to cause these signals to decrease in number. The output signals of the logic circuit are sent to the inspection terminals as monitor signals, based on which an inspection is carried out to determine whether the internal circuit operates normally.

Abstract translation: 高度集成的半导体IC器件包括半导体衬底，内部功能电路布置成具有第一多个输入端子和第二多个输出端子。 逻辑电路布置在基板上，并通过输出端子连接到内部电路。 逻辑电路具有第三多个输出端子，其数量小于内部电路的输出。 这些逻辑输出端子被耦合到相同数量的检查端子，这些检查端子适于联接到已知的电气检查工具。 逻辑电路处理出现在内部电路的输出端子处的电压信号，从而使这些信号数量减少。 逻辑电路的输出信号作为监视信号发送到检查端子，由此执行检查以确定内部电路是否正常工作。

公开(公告)号：US5041700A

公开(公告)日：1991-08-20

申请号：US588928

申请日：1990-09-27

Applicant: Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

Inventor： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

IPC: C04B37/02 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC classification number: C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K3/38

Abstract: A circuit board includes an aluminum nitride substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a metal oxynitride layer represented by formula Al.sub.u Ml.sub.v M2.sub.x O.sub.y N.sub.z (wherein M1 represents a metal selected from the group consisting of Ti, Cr, Ta, and Zr, M2 represents a metal selected from the group consisting of Ni, Pt, Pd, W, Nb, and Mo, u represents 3 to 50 atm %, v represents 3 to 78 atm %, x represents 0 to 50 atm %, y represents 0.005 to 25 atm %, and z represents 5 to 70 atm %), a bonding layer consisting essentially of a metal represented by M1, a barrier layer consisting essentially of a metal represented by M2, and a conductor layer consisting essentially of Au are stacked in the order named.

Abstract translation: 电路板包括氮化铝衬底和形成在衬底上并具有多层结构的电路图案，其中由式AluMlvM2xOyNz表示的金属氧氮化物层（其中M1表示选自Ti，Cr，Ta， Zr，M2表示选自Ni，Pt，Pd，W，Nb和Mo的金属，u表示3〜50atm％，v表示3〜78atm％，x表示0〜50atm％ y表示0.005〜25atm％，z表示5〜70atm％），基本上由M1表示的金属构成的接合层，基本上由M2表示的金属构成的阻挡层和基本上由Au构成的导体层 按照命名的顺序堆叠。

公开(公告)号：US4963701A

公开(公告)日：1990-10-16

申请号：US300944

申请日：1989-01-24

Applicant: Takaaki Yasumoto ,  Nobuo Iwase

Inventor： Takaaki Yasumoto ,  Nobuo Iwase

IPC: H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC classification number: H05K3/388 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/0306

Abstract: Disclosed is an aluminum nitride thin film circuit board having an aluminum nitride substrate and a conductive thin film pattern formed on the substrate. The conductive thin film pattern has a multi-layer structure selected from the group consisting of Ti/Ni/Au, Ti/Pd/Au, Ti/Pt/Au, Ni/Au, Cr/Au, and Cr/Cu/Au, and a boundary layer of Al-N-M-O (M is Ti, Ni, or Cr) is formed between the substrate and the conductive thin film pattern. Since the boundary layer is formed, bonding properties between the substrate and the conductive thin film pattern are improved. In particular, when the boundary layer contains 0.02 to 30 atomic % of oxygen, a higher bonding strength can be obtained.

公开(公告)号：US5008582A

公开(公告)日：1991-04-16

申请号：US515668

申请日：1990-04-26

Applicant: Chiaki Tanuma ,  Kazuhiro Itsumi ,  Nobuo Iwase ,  Tomio Ono ,  Yuu Kondo ,  Kazutaka Saito

Inventor： Chiaki Tanuma ,  Kazuhiro Itsumi ,  Nobuo Iwase ,  Tomio Ono ,  Yuu Kondo ,  Kazutaka Saito

IPC: H01L23/467

CPC classification number: H01L23/467 ,  F04D33/00 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/09701 ,  Y10S310/80

Abstract: In an electric device having a package included an electric circuit element therein, a cooling fan is fixed on the package directly. The fan is formed of piezoelectric elements and a flexible cooling fin. The fan generates the cooling air flow due to vibration of the piezoelectric elements.

Abstract translation: 在具有包括电路元件的封装的电子装置中，冷却风扇直接固定在包装上。 风扇由压电元件和柔性散热片组成。 风扇由于压电元件的振动而产生冷却空气流。

公开(公告)号：US4772985A

公开(公告)日：1988-09-20

申请号：US98240

申请日：1987-09-18

Applicant: Takaaki Yasumoto ,  Osamu Furukawa ,  Nobuo Iwase ,  Mitsuo Harata ,  Masao Segawa

Inventor： Takaaki Yasumoto ,  Osamu Furukawa ,  Nobuo Iwase ,  Mitsuo Harata ,  Masao Segawa

IPC: C04B35/497 ,  C04B35/499 ,  H01G4/12 ,  H01G4/30 ,  C04B35/46 ,  H01G4/10 ,  H01G7/00

CPC classification number: C04B35/499 ,  C04B35/497 ,  H01G4/129 ,  H01G4/30 ,  Y10T29/435

Abstract: Disclosed is a thick film capacitor comprising (a) a sintered layer of a ferroelectric material mainly consisting of one or more ferroelectric inorganic compounds having a perovskite structure and an inorganic binder having a eutectic composition which experiences a liquid phase at a temperature lower than the sintering temperature of the ferroelectric inorganic compounds, and (b) at least two electrodes formed on both surfaces of the sintered layer of the ferroelectric material. In the thick film capacitor of this invention, the perovskite structure of the ferroelectric inorganic compounds is not destroyed upon sintering. Therefore, a high degree of sintering, a good dielectric characteristic and high moisture and migration resistances can be obtained.

Abstract translation: 公开了一种厚膜电容器，其包括（a）主要由具有钙钛矿结构的一种或多种铁电无机化合物和具有在低于烧结温度的温度下经历液相的共晶组成的无机粘合剂的铁电体材料的烧结层 铁电体无机化合物的温度，（b）形成在铁电体的烧结层的两面的至少两个电极。 在本发明的厚膜电容器中，铁电体无机化合物的钙钛矿结构在烧结时不破坏。 因此，可以获得高度的烧结，良好的介电特性和高的湿度和迁移电阻。

公开(公告)号：US4584456A

公开(公告)日：1986-04-22

申请号：US530107

申请日：1983-09-07

Applicant: Hirosi Oodaira ,  Haruko Suzuki ,  Masayuki Saito ,  Nobuo Iwase

Inventor： Hirosi Oodaira ,  Haruko Suzuki ,  Masayuki Saito ,  Nobuo Iwase

IPC: H01C17/00 ,  H01C17/20 ,  H01C17/22 ,  B23K26/00

CPC classification number: H01C17/00 ,  H01C17/20 ,  H01C17/22

Abstract: A resistor is formed by locally heating an insulating material layer between conductors to convert the heated material into a first resistor element. A second resistor element is formed to contact the first resistor element while measuring the resistance between the conductors, until a desired resistor composed of the first and second resistor elements and having a predetermined resistance value is obtained.

Abstract translation: 通过局部加热导体之间的绝缘材料层形成电阻器，将加热的材料转换成第一电阻元件。 第二电阻元件形成为在测量导体之间的电阻的同时接触第一电阻元件，直到获得由第一和第二电阻元件组成并且具有预定电阻值的所需电阻。

公开(公告)号：US4412377A

公开(公告)日：1983-11-01

申请号：US341589

申请日：1982-01-21

Applicant: Kenji Nagashima ,  Hiroshi Matsumoto ,  Masataka Tanaka ,  Hirosi Oodaira ,  Nobuo Iwase

Inventor： Kenji Nagashima ,  Hiroshi Matsumoto ,  Masataka Tanaka ,  Hirosi Oodaira ,  Nobuo Iwase

IPC: H05K3/44 ,  H01L21/48 ,  H01L23/14 ,  H01L23/373 ,  H01L25/16 ,  H05K1/05 ,  H05K3/22 ,  H05K3/28 ,  H05K3/34 ,  H01L21/84

CPC classification number: H05K3/22 ,  H01L21/4846 ,  H01L23/142 ,  H01L23/3735 ,  H01L25/16 ,  H01L2224/48227 ,  H05K1/053 ,  H05K2201/0116 ,  H05K2201/0179 ,  H05K2203/1147 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A method for manufacturing a hybrid integrated circuit device comprising a step of forming an Al.sub.2 O.sub.3 layer on a metal substrate, a step of forming on the Al.sub.2 O.sub.3 layer a resist layer having a pattern opposite to that of a copper layer which will be formed on the Al.sub.2 O.sub.3 layer by a later step, a step of forming the copper layer on the Al.sub.2 O.sub.3 layer using the resist layer as a mask, a step of impregnating thermosetting material into both the Al.sub.2 O.sub.3 layer and the copper layer, and a step of providing at least one semiconductor element on the copper layer.

Abstract translation: 一种制造混合集成电路器件的方法，包括在金属衬底上形成Al 2 O 3层的步骤，在Al 2 O 3层上形成具有与形成在Al 2 O 3上的铜层相反的图案的抗蚀剂层的步骤 使用抗蚀剂层作为掩模在Al2O3层上形成铜层的步骤，将热固性材料浸渍在Al 2 O 3层和铜层中的工序，以及提供至少一个半导体层 元素在铜层上。