公开(公告)号：US20150192949A1

公开(公告)日：2015-07-09

申请号：US14149430

申请日：2014-01-07

Applicant: OmniVision Technologies, Inc.

Inventor： Charles Qingle Wu ,  Min Liu

IPC: G06F1/08 ,  G06F13/40 ,  G06F1/10

CPC classification number: G06F13/40 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0041 ,  H04L7/033

Abstract: A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.

Abstract translation: 移动工业处理器接口（MIPI）物理层（D-PHY）串行通信链路和减少MIPI D-PHY串行通信链路中的时钟数据偏移的方法包括：设备，其包括时钟发送电路，用于在 MIPI D-PHY串行链路的第一通道，用于在MIPI D-PHY串行链路的第二通道上发送数据信号的数据发送电路，用于在MIPI D的第一通道上接收时钟信号的时钟接收电路 -PHY串行链路，以及用于在MIPI D-PHY串行链路的第二通道上接收数据信号的数据接收电路。 时钟发送电路和数据发送电路在正常操作模式期间在校准模式期间同相地发送时钟信号和数据信号。

公开(公告)号：US20210329185A1

公开(公告)日：2021-10-21

申请号：US16854765

申请日：2020-04-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Yu-Shen Yang ,  Charles Qingle Wu

IPC: H04N5/378 ,  H03M7/16 ,  H03M1/56

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

公开(公告)号：US10312887B2

公开(公告)日：2019-06-04

申请号：US15365605

申请日：2016-11-30

Applicant: OmniVision Technologies, Inc.

Inventor： Li Yang ,  Charles Qingle Wu

IPC: H03B5/24 ,  H03K3/36 ,  H03K4/50 ,  H03K3/011 ,  H03K3/012 ,  H03K3/037 ,  H03K3/354 ,  H03K3/0231

Abstract: An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.

公开(公告)号：US10175715B2

公开(公告)日：2019-01-08

申请号：US15272145

申请日：2016-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Li Yang ,  Zhenhua Zhu

IPC: G06F3/00 ,  G06F13/42 ,  G06F1/08 ,  H04N5/374

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

公开(公告)号：US20180081389A1

公开(公告)日：2018-03-22

申请号：US15272145

申请日：2016-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Li Yang ,  Zhenhua Zhu

IPC: G06F1/08 ,  G06F13/42

CPC classification number: G06F1/08 ,  G06F3/005 ,  G06F13/4291 ,  H04N5/374

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

公开(公告)号：US11431936B2

公开(公告)日：2022-08-30

申请号：US16854765

申请日：2020-04-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Yu-Shen Yang ,  Charles Qingle Wu

IPC: H03M1/12 ,  H04N5/378 ,  H03M7/16 ,  H03M1/56 ,  H03K19/21 ,  H03K19/20

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

公开(公告)号：US09900145B2

公开(公告)日：2018-02-20

申请号：US15159583

申请日：2016-05-19

Applicant: OmniVision Technologies, Inc.

Inventor： Li Yang ,  Wengen Wang ,  Charles Qingle Wu

IPC: H03D3/24 ,  H04L7/033 ,  H04L5/00 ,  H04B1/69

CPC classification number: H04L7/0331 ,  G06F1/08 ,  H03K3/84 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/131 ,  H03K5/133 ,  H03K5/14 ,  H03L7/16 ,  H04B1/69 ,  H04B15/02 ,  H04L5/005

Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

公开(公告)号：US09608633B1

公开(公告)日：2017-03-28

申请号：US14951307

申请日：2015-11-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Min Liu ,  Yun Hak Koh ,  Charles Qingle Wu

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/0013 ,  H03K19/018514

Abstract: An interface circuit includes a pre-driver that converts the single-ended signal to an intermediate differential signal having a first voltage swing responsive to a first supply voltage supplied to the pre-driver. An output driver is coupled to receive the intermediate differential signal from the pre-driver to convert the intermediate differential signal to an output differential signal coupled to be received by a load coupled to the output driver. The output differential signal has a second voltage swing responsive to a second supply voltage supplied to the output driver. An internal regulator is coupled to receive a variable supply voltage to supply the second voltage to the output driver. The second supply voltage is generated in response to a bias signal. A replica bias circuit is coupled to receive the variable supply voltage to generate the bias signal.

公开(公告)号：US09513655B1

公开(公告)日：2016-12-06

申请号：US14951317

申请日：2015-11-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Min Liu ,  Po-Chia Lai ,  Charles Qingle Wu

IPC: G05F5/00 ,  H03K17/687

CPC classification number: G05F5/00 ,  H04L25/00

Abstract: An interface circuit includes a pre-driver coupled convert a single-ended signal to an intermediate differential signal. An output driver is coupled to convert the intermediate differential signal to an output differential signal having a variable output swing responsive to a mode select signal and a second supply voltage. A replica bias circuit is coupled to receive a first supply voltage, the mode select signal, and an open termination enable signal to generate a bias signal. An internal regulator is coupled to receive the bias signal and the first supply voltage to supply the second voltage to the output driver in response to the bias signal. An open termination circuit is coupled to an output of the output driver, and is coupled to receive the open termination enable signal to couple an internal load to the output of the output driver in response to the open termination enable signal.

Abstract translation: 接口电路包括预驱动器，将单端信号耦合到中间差分信号。 输出驱动器被耦合以响应于模式选择信号和第二电源电压将中间差分信号转换成具有可变输出摆幅的输出差分信号。 复制偏置电路被耦合以接收第一电源电压，模式选择信号和开放终止使能信号以产生偏置信号。 耦合内部稳压器以接收偏置信号和第一电源电压，以响应于偏置信号将第二电压提供给输出驱动器。 开放终端电路耦合到输出驱动器的输出端，并被耦合以响应于开放终止使能信号而接收打开终止使能信号以将内部负载耦合到输出驱动器的输出端。

公开(公告)号：US20140132592A1

公开(公告)日：2014-05-15

申请号：US13673856

申请日：2012-11-09

Applicant: OmniVision Technologies, Inc.

Inventor： Min Liu ,  Yun Hak Koh ,  Charles Qingle Wu

IPC: H04B1/04 ,  G09G5/00

CPC classification number: H04B1/04 ,  G09G5/006 ,  G09G2310/0289 ,  G09G2370/08 ,  H04L25/02 ,  H04L25/0272 ,  H04L25/0286 ,  H04N9/00

Abstract: A transmitter for generating a differential signal pair including a pre-emphasis component. In an embodiment, the transmitter comprises pre-driver circuitry including an input to receive a single-ended data signal. The differential transmitter further comprises a load circuit coupled between the input and a node coupled to an output of the pre-driver circuitry which corresponds to a constituent signal of the differential signal pair. In another embodiment, the load circuit is configurable to provide a signal path between the input and the node. A configuration of the load circuit allows for a type of pre-emphasis to be included in the constituent signal.

Abstract translation: 一种用于产生包括预加重分量的差分信号对的发射机。 在一个实施例中，发射机包括预驱动器电路，其包括用于接收单端数据信号的输入。 差分发射器还包括耦合在输入端和耦合到预驱动器电路的输出端的节点之间的负载电路，其对应于差分信号对的构成信号。 在另一个实施例中，负载电路可配置为在输入和节点之间提供信号路径。 负载电路的配置允许将一种预加重包括在组成信号中。