公开(公告)号：US20220320026A1

公开(公告)日：2022-10-06

申请号：US17213875

申请日：2021-03-26

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Rong ZHOU ,  Li-Sheng WENG ,  Lily ZHAO

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

公开(公告)号：US20240421128A1

公开(公告)日：2024-12-19

申请号：US18335532

申请日：2023-06-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Yi-Hang LIN ,  Dongming HE ,  Lily ZHAO ,  Ryan LANE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L27/02

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

公开(公告)号：US20220270995A1

公开(公告)日：2022-08-25

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei HU ,  Dongming HE ,  Wen YIN ,  Zhe GUAN ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

公开(公告)号：US20230369234A1

公开(公告)日：2023-11-16

申请号：US17741986

申请日：2022-05-11

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Srikanth KULKARNI ,  Lily ZHAO ,  Milind SHAH

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/165 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/32

Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.

公开(公告)号：US20230369230A1

公开(公告)日：2023-11-16

申请号：US17742001

申请日：2022-05-11

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Manuel ALDRETE ,  Lily ZHAO

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/5383 ,  H01L24/08 ,  H01L23/3107 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L21/56

Abstract: A package comprising a first metallization portion, a first integrated device, an interconnection die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnection die is coupled to the first metallization portion. The second metallization portion coupled to the first metallization portion through the interconnection die such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects. The encapsulation layer coupled to the first metallization portion and the second metallization portion, wherein the encapsulation layer is located between the first metallization portion and the second metallization portion.

公开(公告)号：US20240371806A1

公开(公告)日：2024-11-07

申请号：US18313020

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Jun CHEN ,  Yangyang SUN ,  Lily ZHAO ,  Ahmer SYED

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

公开(公告)号：US20240055383A1

公开(公告)日：2024-02-15

申请号：US17819269

申请日：2022-08-11

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Lily ZHAO

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/04 ,  H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/03912 ,  H01L2224/0345 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/11849 ,  H01L2224/11462 ,  H01L2224/11912

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

公开(公告)号：US20210210449A1

公开(公告)日：2021-07-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Wei HU ,  Wei WANG ,  Lily ZHAO

IPC: H01L23/00

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US20240355781A1

公开(公告)日：2024-10-24

申请号：US18628469

申请日：2024-04-05

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Xuefeng ZHANG ,  Jun CHEN ,  Lily ZHAO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/1306 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A device includes an integrated device. The integrated device includes a die that is at least partially encapsulated. The die includes a conductive pad. The device also includes a first passivation layer coupled to a first surface of the die. The device includes an offset interconnect extending along a surface of the first passivation layer and including a portion that extends through an opening in the first passivation layer to contact the conductive pad. The device includes a bump including a portion that extends through an opening in a second passivation layer to contact the offset interconnect. The bump is offset, in a direction along a surface of the second passive layer, from the conductive pad.

公开(公告)号：US20230384367A1

公开(公告)日：2023-11-30

申请号：US17804658

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Amer Christophe Gaetan CASSIER ,  Stanley Seungchul SONG ,  Lily ZHAO ,  Dongming HE

IPC: G01R31/28 ,  H01L23/00

CPC classification number: G01R31/2884 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2924/1431 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14515 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/11916 ,  H01L2224/11903 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/13005 ,  H01L2224/13016

Abstract: Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.