公开(公告)号：US20230411320A1

公开(公告)日：2023-12-21

申请号：US18303983

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L23/00 ,  H01L29/45 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L2224/06181 ,  H01L29/401 ,  H01L24/03 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05638 ,  H01L2924/01014 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/13055 ,  H01L24/48 ,  H01L2224/48245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/03848 ,  H01L2224/04042 ,  H01L24/32 ,  H01L2224/32245 ,  H01L24/73 ,  H01L2224/73265 ,  H01L24/06 ,  H01L29/45

Abstract: A metal film, a manufacturing method of the metal film, semiconductor device, and a manufacturing method of semiconductor device are provided with high crack resistance (higher hardness) during wire bonding. The Metal film has first metal crystal grains, and the second metal crystal grains. Each of the first metal crystal grains has dislocations. Each of the second metal crystal grains has no dislocations. The number of the first metal crystal grains having the dislocations is larger than the number of the second metal crystal grains having no dislocations.

公开(公告)号：US20170069648A1

公开(公告)日：2017-03-09

申请号：US15259502

申请日：2016-09-08

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/115 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/285 ,  H01L21/321 ,  H01L21/28 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: When upper surfaces of a control gate electrode and a memory gate electrode are exposed from an interlayer insulating film by polishing the interlayer insulating film in a gate last process, a silicide layer covering the upper surfaces of the gate electrodes is formed. Thereafter, by reacting a metal film deposited on the silicide layer with the control gate electrode and the memory gate electrode, a silicide layer thicker than the former silicide layer is formed on each of the gate electrodes.

Abstract translation: 通过在栅极最后工艺中研磨层间绝缘膜，在控制栅电极和存储栅电极的上表面从层间绝缘膜露出，形成覆盖栅电极的上表面的硅化物层。 此后，通过使沉积在硅化物层上的金属膜与控制栅电极和存储栅电极反应，在每个栅电极上形成比先前的硅化物层厚的硅化物层。

公开(公告)号：US20240349509A1

公开(公告)日：2024-10-17

申请号：US18595236

申请日：2024-03-04

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H10B51/30 ,  H01L21/28 ,  H01L29/51

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/516

Abstract: A performance of a semiconductor device is improved. A gate insulating film is formed on a semiconductor substrate. A gate electrode is formed on the gate insulating film. A ferroelectric film and a metal film are formed between the gate insulating film and the gate electrode. A thickness of the metal film is smaller than a thickness of the ferroelectric film. The metal film is amorphous.

公开(公告)号：US20240120406A1

公开(公告)日：2024-04-11

申请号：US18449763

申请日：2023-08-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI ,  Yoshiki MARUYAMA

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/66348 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28211

Abstract: It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.

公开(公告)号：US20210249515A1

公开(公告)日：2021-08-12

申请号：US17222534

申请日：2021-04-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/28 ,  H01L29/78 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/51

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

公开(公告)号：US20200279856A1

公开(公告)日：2020-09-03

申请号：US16805447

申请日：2020-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/78 ,  H01L29/792 ,  H01L21/285 ,  H01L29/66

Abstract: In a semiconductor device having MONOS memories configured by fin-type MISFETs, an increase in parasitic capacitance between wirings accompanying miniaturization of the semiconductor device is prevented, and the reliability of the semiconductor device is improved. In a memory cell array in which a plurality of MONOS type memory cells formed on fins are arranged, source regions formed on the plurality of fins arranged in a short direction of the fin are electrically connected to each other by one epitaxial layer straddling the fins.

公开(公告)号：US20180197768A1

公开(公告)日：2018-07-12

申请号：US15916615

申请日：2018-03-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L21/764 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3081 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

公开(公告)号：US20170358592A1

公开(公告)日：2017-12-14

申请号：US15482239

申请日：2017-04-07

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/324 ,  H01L21/67 ,  H01L29/49 ,  H01L29/06 ,  H01L21/762 ,  H01L29/08 ,  H01L21/285 ,  H01L29/792 ,  H01L29/10 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/324 ,  H01L21/67167 ,  H01L21/76224 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

Abstract: Resistance of a FINFET is reduced while performance of an element is prevented from being deteriorated due to an increase in stress, thereby performance of a semiconductor device is improved. When a memory cell formed on an upper side of a first fin and an n transistor formed on an upper side of a second fin are mounted on the same semiconductor substrate, the surface of the first fin having a source/drain region of the memory cell is covered with a silicide layer, and part of a source/drain region of the n transistor is formed of an epitaxial layer covering the surface of the second fin.

公开(公告)号：US20170018591A1

公开(公告)日：2017-01-19

申请号：US15168371

申请日：2016-05-31

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/146

CPC classification number: H01L27/14638 ,  H01L27/14605 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14689

Abstract: An image pickup device capable of completely transmit charges generated at a photodiode to a floating diffusion region is provided. In a pixel region, a plurality of fin-like structures are so formed as to loin a photodiode formation region with the floating diffusion region. In the fin-like structure, a depth from a surface of a P type well to a predetermined position of depth is defined as a “height.” Having the height and a width, the fin-like structure extends in a direction intersecting a direction in which a gate electrode extends. The gate electrode of a transfer transistor is so formed as to cover opposing side surfaces and an upper surface of each fin-like structure.

Abstract translation: 提供能够将在光电二极管处产生的电荷完全传输到浮动扩散区域的图像拾取装置。 在像素区域中，多个鳍状结构形成为具有浮动扩散区域的光电二极管形成区域。 在翅片状结构中，从P型阱的表面到深度的预定位置的深度被定义为“高度”。具有高度和宽度，鳍状结构在与方向相交的方向上延伸 其中栅电极延伸。 转移晶体管的栅极形成为覆盖相对的侧表面和每个鳍状结构的上表面。

公开(公告)号：US20160218125A1

公开(公告)日：2016-07-28

申请号：US14992103

申请日：2016-01-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14612 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14689 ,  H01L27/14698

Abstract: Object is to prevent deterioration in pixel characteristics due to dark-time white spot defects in a pixel. Generation of these dark-time white spot defects is attributable to diffusion of electrons and Fe (iron) from the vicinity of an interface between a semiconductor substrate and an element isolation region obtained by filling a trench formed in the upper surface of the semiconductor substrate with an insulating film. A semiconductor layer is formed by forming, in the upper surface of a semiconductor substrate, a trench for filling it with an element isolation region surrounding a photodiode formation region; and carrying out plasma doping to introduce B (boron) into the side wall and bottom surface of the trench.

Abstract translation: 目的在于防止由于像素中的暗时白斑缺陷引起的像素特性的劣化。 这些黑暗时间白点缺陷的产生可归因于电子和Fe（铁）从半导体衬底和元件隔离区之间的界面附近的扩散，这是通过用形成在半导体衬底的上表面中的沟槽填充而获得的元件隔离区 绝缘膜。 半导体层通过在半导体衬底的上表面中形成用于用围绕光电二极管形成区域的元件隔离区填充沟槽而形成的沟槽; 并进行等离子体掺杂以将B（硼）引入沟槽的侧壁和底表面。