公开(公告)号：US10153207B2

公开(公告)日：2018-12-11

申请号：US15194309

申请日：2016-06-27

Applicant: STMicroelectronics S.R.L.

Inventor： Ferruccio Frisina ,  Giuseppe Abbondanza

IPC: C30B25/10 ,  H01L21/78 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C23C16/01 ,  C23C16/02 ,  C23C16/32 ,  C23C16/458

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

公开(公告)号：US09911810B2

公开(公告)日：2018-03-06

申请号：US15421100

申请日：2017-01-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/324 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L29/872 ,  H01L29/04

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

公开(公告)号：US09607859B2

公开(公告)日：2017-03-28

申请号：US14788685

申请日：2015-06-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/73 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

公开(公告)号：US08895370B2

公开(公告)日：2014-11-25

申请号：US14042041

申请日：2013-09-30

Applicant: STMicroelectronics S.R.L.

Inventor： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri′

IPC: H01L21/332 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/861 ,  H01L29/732 ,  H01L29/739 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.

Abstract translation: 垂直导通功率器件包括形成在半导体衬底上的外延层中的相应的栅极，源极和漏极区域。 相应的栅极，源极和漏极金属化由第一金属化层形成。 栅极，源极和漏极端子由第二金属化层形成。 该设备被配置为彼此平行延伸的一组模块区域。 每个模块区域具有由栅极区域周边包围的矩形细长源区域和由第一和第二区域限定的漏极区域。 排水的第一区域彼此平行延伸并分开相邻的模块区域。 漏极区域的第二区域彼此平行延伸并且与漏极区域的第一区域的端部接触。

公开(公告)号：US09406504B2

公开(公告)日：2016-08-02

申请号：US13714277

申请日：2012-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio Frisina ,  Giuseppe Abbondanza

IPC: C30B25/12 ,  H01L21/02 ,  C30B33/00 ,  C30B33/06 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C23C16/01 ,  C23C16/02 ,  C23C16/32

CPC classification number: H01L21/7806 ,  C23C16/01 ,  C23C16/0218 ,  C23C16/325 ,  C23C16/4583 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02609

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract translation: 本文所述的实施例包括用于制造第一半导体材料的晶片的方法。 所述第一半导体材料具有第一熔融温度。 该方法包括提供具有低于第一熔融温度的第二熔融温度的第二半导体材料的晶体衬底，以及将晶体衬底暴露于第一材料前体流，以在衬底上形成第一材料的第一层。 所述方法还包括使所述晶体衬底处于比所述第二熔化温度高的第一工艺温度，并且同时低于所述第一熔化温度，以这种方式，所述第二材料熔化，将所述第二熔化材料与所述第一熔化层分离 并且将第一层暴露于第一材料前体的流动，以在第一层上形成第一材料的第二层。

公开(公告)号：US20130157448A1

公开(公告)日：2013-06-20

申请号：US13714277

申请日：2012-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio Frisina ,  Giuseppe Abbondanza

IPC: H01L21/02

CPC classification number: H01L21/7806 ,  C23C16/01 ,  C23C16/0218 ,  C23C16/325 ,  C23C16/4583 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02609

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract translation: 本文所述的实施例包括用于制造第一半导体材料的晶片的方法。 所述第一半导体材料具有第一熔融温度。 该方法包括提供具有低于第一熔融温度的第二熔融温度的第二半导体材料的晶体衬底，以及将晶体衬底暴露于第一材料前体流，以在衬底上形成第一材料的第一层。 所述方法还包括使所述晶体衬底处于比所述第二熔化温度高的第一工艺温度，并且同时低于所述第一熔化温度，以这种方式，所述第二材料熔化，将所述第二熔化材料与所述第一熔化层分离 并且将第一层暴露于第一材料前体的流动，以在第一层上形成第一材料的第二层。

公开(公告)号：US08580640B2

公开(公告)日：2013-11-12

申请号：US13706312

申请日：2012-12-05

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti ,  Ferruccio Frisina

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

Abstract translation: 一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。 该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二掩模; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

公开(公告)号：US20170141191A1

公开(公告)日：2017-05-18

申请号：US15421100

申请日：2017-01-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simona Lorenti ,  Cateno Marco Camalleri ,  Mario Giuseppe Saggio ,  Ferruccio Frisina

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

公开(公告)号：US09142646B2

公开(公告)日：2015-09-22

申请号：US14645185

申请日：2015-03-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferruccio Frisina ,  Angelo Magri′ ,  Mario Giuseppe Saggio

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/402 ,  H01L29/66431 ,  H01L29/7811 ,  H01L29/7813

Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

公开(公告)号：US20160307800A1

公开(公告)日：2016-10-20

申请号：US15194309

申请日：2016-06-27

Applicant: STMicroelectronics S.R.L.

Inventor： Ferruccio Frisina ,  Giuseppe Abbondanza

IPC: H01L21/78 ,  C23C16/32 ,  C23C16/01 ,  H01L21/02 ,  C23C16/458

CPC classification number: H01L21/7806 ,  C23C16/01 ,  C23C16/0218 ,  C23C16/325 ,  C23C16/4583 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02609

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.