公开(公告)号：US20160268418A1

公开(公告)日：2016-09-15

申请号：US15165372

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  G11C14/00 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

公开(公告)号：US09099304B2

公开(公告)日：2015-08-04

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/318 ,  H01L21/02 ,  H01L29/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US20150028458A1

公开(公告)日：2015-01-29

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Rakib Uddin Mohammad ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US10141407B2

公开(公告)日：2018-11-27

申请号：US14506041

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Seong-ho Cho

IPC: H01L27/108 ,  H01L29/66 ,  H01L45/00 ,  H01L29/16 ,  H01L29/68 ,  H01L27/105 ,  H01L29/76

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

公开(公告)号：US09929239B2

公开(公告)日：2018-03-27

申请号：US15050867

申请日：2016-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

IPC: H01L29/51 ,  H01L29/34 ,  H01L29/66 ,  H01L29/20 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/24

CPC classification number: H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

公开(公告)号：US09379319B2

公开(公告)日：2016-06-28

申请号：US14444083

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/02 ,  H01L45/00 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract translation: 提供了非易失性存储晶体管和包括非易失性存储晶体管的器件。 非易失性存储晶体管可以包括沟道元件，对应于沟道元件的栅极电极，沟道元件和栅电极之间的栅极绝缘层，栅极绝缘层和栅电极之间的离子物质移动层，以及源极 以及相对于沟道元件彼此分离的漏极。 根据施加到栅电极的电压，发生离子物质移动层处的离子物质的运动。 阈值电压根据离子物质的运动而变化。 非易失性存储晶体管具有多电平特性。

公开(公告)号：US09207469B2

公开(公告)日：2015-12-08

申请号：US13973521

申请日：2013-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-seung Yang ,  Seong-ho Cho ,  Mohammad Rakib Uddin

IPC: G02F1/035 ,  G02F1/025

CPC classification number: G02F1/025 ,  G02F2203/60 ,  Y02E10/50

Abstract: An athermal optical modulator includes a waveguide, a ring resonator configured to receive light input from the waveguide and output modulated light to the waveguide, the ring resonator including a ridge unit located at a center of the ring resonator in a vertical section, a first contact connected to one side of the ridge unit and a second contact connected to the other side of the ridge unit, the first contact and the second contact forming paths for applying electricity to the ring resonator to form an electric field in the ring resonator, and a polymer layer covering the ridge unit.

Abstract translation: 一种无热光调制器，包括波导，环形谐振器，其被配置为接收从波导输入的光并将调制光输出到波导，所述环形谐振器包括位于所述环形谐振器的垂直部分的中心的脊单元，所述第一接触 连接到所述脊单元的一侧，并且连接到所述脊单元的另一侧的第二触点，所述第一触点和所述第二触点形成路径用于向所述环形谐振器施加电力以在所述环形谐振器中形成电场，以及 覆盖脊单元的聚合物层。

公开(公告)号：US20150061030A1

公开(公告)日：2015-03-05

申请号：US14471900

申请日：2014-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mohammad Rakib Uddin ,  Moon-seung Yang ,  Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Eui-chul Hwang

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/16 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/04 ,  H01L21/02381 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76224 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20

Abstract: Provided are semiconductor structures and methods of fabricating the same. The semiconductor structure includes a silicon substrate, at least one semiconductor layer that is grown on the silicon substrate and has a lattice constant in a range from about 1.03 to about 1.09 times greater than that of the silicon substrate, and a buffer layer that is disposed between the silicon substrate and the semiconductor layer and includes a metal silicide compound for lattice matching with the semiconductor layer. Related fabrication methods are also discussed.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括硅衬底，至少一个在硅衬底上生长并具有比硅衬底大约1.03至大约1.09倍的晶格常数的半导体层，以及设置的缓冲层 在硅衬底和半导体层之间，并且包括用于与半导体层进行晶格匹配的金属硅化物化合物。 还讨论了相关的制造方法。

公开(公告)号：US09097845B2

公开(公告)日：2015-08-04

申请号：US13768204

申请日：2013-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-ho Cho

IPC: G02B6/12 ,  H01L21/82 ,  G02B6/134

CPC classification number: G02B6/12 ,  G02B6/1347 ,  G02B6/4214 ,  G02B2006/12104 ,  H01L21/82

Abstract: An optoelectronic chip, and/or a method of manufacturing the same, include a substrate; a coupler region surrounded by the substrate. The coupler region includes a total reflection surface. The total reflection surface is configured to totally reflect a first light incident through a surface of the substrate such that the reflected first light travels within the substrate, or the total reflection surface is configured to totally reflect a second light guided in the substrate and incident on the total reflecting surface such that the reflected second light travels through the surface of the substrate.

Abstract translation: 光电子芯片和/或其制造方法包括：基板; 由衬底包围的耦合器区域。 耦合器区域包括全反射面。 全反射面被配置为完全反射通过基板的表面入射的第一光，使得反射的第一光在基板内行进，或者全反射表面被配置为完全反射在基板中引导的第二光并入射到 全反射表面使得反射的第二光穿过基板的表面。

公开(公告)号：US08862749B2

公开(公告)日：2014-10-14

申请号：US13739563

申请日：2013-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-ho Cho ,  Se-hee Han ,  Je-young Maeng

IPC: G06F15/16 ,  H04L29/12 ,  H04L29/06 ,  H04L29/08 ,  H04L12/28

CPC classification number: H04L41/28 ,  G06F9/452 ,  H04L12/2809 ,  H04L12/2818 ,  H04L29/125 ,  H04L29/12509 ,  H04L61/2564 ,  H04L61/2567 ,  H04L61/2578 ,  H04L65/1006 ,  H04L67/02 ,  H04L67/025 ,  H04L67/30 ,  H04W76/10 ,  H04W76/12

Abstract: A remote access service is provided by receiving remote access transport agent (RATA) capability information of a home remote access server (RAS) and a remote RAS from the home RAS and the remote RAS, respectively, generating a RATA profile based on the RATA capability information, supported by the home RAS and the remote RAS, and transmitting the generated RATA profile to the home RAS and the remote RAS, respectively.

Abstract translation: 通过分别从家庭RAS和远程RAS接收归属远程访问服务器（RAS）和远程RAS的远程访问传输代理（RATA）能力信息来分别提供远程访问服务，以基于RATA能力生成RATA简档 信息，由家庭RAS和远程RAS支持，并且将生成的RATA简档分别发送到归属RAS和远程RAS。