公开(公告)号：US11785767B2

公开(公告)日：2023-10-10

申请号：US17159727

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US20170148804A1

公开(公告)日：2017-05-25

申请号：US15426081

申请日：2017-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Youngwoo Kim ,  Jinhyun Shin ,  Jung Hoon Lee

IPC: H01L27/11573 ,  H01L27/11582

CPC classification number: H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

公开(公告)号：US20240055493A1

公开(公告)日：2024-02-15

申请号：US18364521

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Kyoungwoo Lee ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a fin-type active pattern, source/drain regions on the fin-type active pattern, an interlayer insulating layer on the isolation insulating layer, and on the source/drain region, a contact structure electrically connected to the source/drain regions, a buried conductive structure electrically connected to the contact structure and buried in the interlayer insulating layer, and a power delivery structure that penetrates the substrate, and is in contact with a bottom surface of the buried conductive structure. The buried conductive structure includes a first contact plug, and a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom surface of the first contact plug. The power delivery structure includes a second contact plug in direct contact with the bottom surface of the first contact plug.

公开(公告)号：US20230411157A1

公开(公告)日：2023-12-21

申请号：US18136407

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungkyo Lee ,  Jongin Kang ,  Gyeyoung Kim ,  Youngwoo Kim ,  Yonghan Park ,  Woojin Jung ,  Seunguk Han ,  Juyoung Huh

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/16 ,  H01L23/544

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/0228 ,  H01L23/16 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.

公开(公告)号：US09911745B2

公开(公告)日：2018-03-06

申请号：US15426081

申请日：2017-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Youngwoo Kim ,  Jinhyun Shin ,  Jung Hoon Lee

IPC: H01L27/11551 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11 ,  H01L27/11556 ,  H01L27/108 ,  H01L27/11529 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/115 ,  H01L21/8234 ,  H01L27/11597

CPC classification number: H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

公开(公告)号：US12114497B2

公开(公告)日：2024-10-08

申请号：US18464668

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US12101937B2

公开(公告)日：2024-09-24

申请号：US18358993

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Jeong ,  Youngwoo Kim ,  Jaesung Kim ,  Hyoungryeol In

IPC: H10B43/50 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/50 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate in the first region and extending in different lengths along a second direction, perpendicular to the first direction in the second region, first separation regions penetrating the gate electrodes in the first and second regions, extending in the second direction, and spaced apart from each other in a third direction, perpendicular to the first and second directions, second separation regions penetrating the gate electrodes in the second region and spaced apart from each other in the second direction between the separation regions, and a first vertical structure penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation regions in the third direction is greater than a width of the first vertical structure, a first end point of the second separation regions adjacent to the first region is spaced apart from a central axis of the first dummy structure in the second direction, away from the first region.

公开(公告)号：US20240047306A1

公开(公告)日：2024-02-08

申请号：US18220971

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongick Anthony LEE ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Sangcheol Last Name not provide

IPC: H01L23/48 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/66545

Abstract: A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

公开(公告)号：US20230422497A1

公开(公告)日：2023-12-28

申请号：US18464668

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US20240381643A1

公开(公告)日：2024-11-14

申请号：US18616343

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Juyeon Jung ,  Byoungtaek Kim ,  Gwangwe Yoo

IPC: H10B43/27 ,  H01L23/00 ,  H10B41/27

Abstract: A semiconductor device includes a gate electrode structure including gate electrodes spaced apart in a first direction perpendicular to an upper surface of a substrate, each gate electrode extending in a second direction parallel to the upper surface of the substrate, a memory channel structure, and a support pattern array including support patterns spaced apart in the second direction and a third direction crossing the second direction, wherein each support pattern has a shape including three vertices and three sides, and wherein a first vertex of a first support pattern closest to a second support pattern and a first vertex of the second support pattern closest to the first support pattern are not aligned in the third direction but have different positions in the second direction.