-
1.发明申请公开(公告)号：US20200350285A1
公开(公告)日：2020-11-05
申请号：US16554779
申请日：2019-08-29
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Ching Ho , Bo-Hao Ma , Yu-Ting Xue , Ching-Hung Tseng , Guan-Hua Lu , Hong-Da Chang
IPC: H01L25/065 , H01L23/31 , H01L23/522 , H01L23/00 , H01L21/56 , H01L21/48
Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
-
公开(公告)号：US20150305162A1
公开(公告)日：2015-10-22
申请号：US14461828
申请日：2014-08-18
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shao-tzu Tang , Chi-Ching Ho , Ying-Chou Tsai
CPC classification number: H05K1/186 , H01L23/49822 , H01L23/50 , H01L28/40 , H01L2924/0002 , H05K1/115 , H05K3/10 , H05K3/42 , H05K2201/10015 , H05K2203/0733 , H01L2924/00
Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.
Abstract translation: 提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。 每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。 取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。
-
公开(公告)号：US12199047B2
公开(公告)日：2025-01-14
申请号：US17572001
申请日：2022-01-10
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chao-Chiang Pu , Chi-Ching Ho , Yi-Min Fu , Yu-Po Wang , Po-Yuan Su
IPC: H01L23/00 , H01L21/48 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/58 , H01L23/42 , H05K1/02
Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
-
公开(公告)号：US20240038685A1
公开(公告)日：2024-02-01
申请号：US17950914
申请日：2022-09-22
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chao-Chiang Pu , Chi-Ching Ho , Yi-Min Fu , Yu-Po Wang , Fang-Lin Tsai
IPC: H01L23/00 , H01L25/10 , H01L23/498 , H01L23/538 , H01L21/48
CPC classification number: H01L23/562 , H01L24/16 , H01L24/73 , H01L24/32 , H01L25/105 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/5381 , H01L23/5385 , H01L23/5386 , H01L21/4817 , H01L2924/37001 , H01L2924/3511 , H01L2224/73204 , H01L2224/32225 , H01L2224/16227 , H01L2224/16238 , H01L2224/16235
Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.
-
公开(公告)号：US20190043819A1
公开(公告)日：2019-02-07
申请号：US15869249
申请日：2018-01-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Ching Ho , Ying-Chou Tsai
Abstract: An electronic package is provided, including an electronic component, a redistribution structure formed on the electronic component, a plurality of conductive posts bonded to the redistribution structure, and a redistribution layer bonded to the conductive posts. As such, the electronic component that meets the requirement of miniaturization can be electrically connected to an electronic device through the redistribution structure, the conductive posts and the redistribution layer.
-
Patent Agency Ranking
公开(公告)号：US20170047230A1
公开(公告)日：2017-02-16
申请号：US15293858
申请日：2016-10-14
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Ching Ho , Ying-Chou Tsai , Sheng-Che Huang
IPC: H01L21/48 , H01L23/00 , H05K3/46 , H05K3/06 , H05K3/34 , H01L21/683 , H01L23/498 , H05K3/40
CPC classification number: H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/16 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/16238 , H01L2224/81193 , H05K3/064 , H05K3/205 , H05K3/3436 , H05K3/4007 , H05K3/4038 , H05K3/4682 , H05K2201/0376 , Y02P70/613 , Y10T29/49158
Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
Abstract translation: 公开了一种封装基板，包括：介电层; 电介质层，其中所述电路层嵌入并暴露于所述电介质层的表面，其中所述电路层具有多个导电焊盘; 以及形成在所述导电焊盘上并突出在所述电介质层的表面上方的多个导电凸块。 这样，当通过多个导电元件将电子元件设置在导电焊盘上时，导电元件可以与导电凸块的顶表面和侧表面接触，从而增加导电元件与导电元件之间的接触面积 导电焊盘，从而加强导电元件和导电焊盘之间的接合，并防止导电元件与导电焊盘分层。
-
公开(公告)号：US20150144384A1
公开(公告)日：2015-05-28
申请号：US14104514
申请日：2013-12-12
Applicant: Siliconware Precision Industries Co., Ltd
Inventor： Chi-Ching Ho , Ying Chou Tsai , Sheng-Che Huang
CPC classification number: H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/16 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/16238 , H01L2224/81193 , H05K3/064 , H05K3/205 , H05K3/3436 , H05K3/4007 , H05K3/4038 , H05K3/4682 , H05K2201/0376 , Y02P70/613 , Y10T29/49158
Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
Abstract translation: 公开了一种封装基板，包括：介电层; 电介质层，其中所述电路层嵌入并暴露于所述电介质层的表面，其中所述电路层具有多个导电焊盘; 以及形成在所述导电焊盘上并突出在所述电介质层的表面上方的多个导电凸块。 这样，当通过多个导电元件将电子元件设置在导电焊盘上时，导电元件可以与导电凸块的顶表面和侧表面接触，从而增加导电元件与导电元件之间的接触面积 导电焊盘，从而加强导电元件和导电焊盘之间的接合，并防止导电元件与导电焊盘分层。
-
公开(公告)号：US20220399246A1
公开(公告)日：2022-12-15
申请号：US17829533
申请日：2022-06-01
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Yi-Min Fu , Chi-Ching Ho , Yu-Po Wang
IPC: H01L23/373 , H01L23/00 , H01L23/31 , H01L23/498 , H01L21/56
Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.
-
公开(公告)号：US09991197B2
公开(公告)日：2018-06-05
申请号：US15632669
申请日：2017-06-26
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chia-Cheng Chen , Chi-Ching Ho , Shao-Tzu Tang , Yu-Che Liu , Ying-Chou Tsai
CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/56 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49894 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L2221/68345 , H01L2224/05554 , H01L2224/16227 , H01L2224/16238 , H01L2224/2929 , H01L2224/29339 , H01L2224/32225 , H01L2224/45144 , H01L2224/48159 , H01L2224/48227 , H01L2224/48247 , H01L2224/49173 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2224/81193 , H01L2224/81424 , H01L2224/81447 , H01L2224/83005 , H01L2224/85005 , H01L2924/00014 , H01L2924/10162 , H01L2924/181 , H01L2924/35121 , H01L2224/13099 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
-
公开(公告)号：US20170033037A1
公开(公告)日：2017-02-02
申请号：US15293883
申请日：2016-10-14
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Ching Ho , Ying-Chou Tsai , Sheng-Che Huang
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/16 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/16238 , H01L2224/81193 , H05K3/064 , H05K3/205 , H05K3/3436 , H05K3/4007 , H05K3/4038 , H05K3/4682 , H05K2201/0376 , Y02P70/613 , Y10T29/49158
Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
Abstract translation: 公开了一种封装基板，包括：介电层; 电介质层，其中所述电路层嵌入并暴露于所述电介质层的表面，其中所述电路层具有多个导电焊盘; 以及形成在所述导电焊盘上并突出在所述电介质层的表面上方的多个导电凸块。 这样，当通过多个导电元件将电子元件设置在导电焊盘上时，导电元件可以与导电凸块的顶表面和侧表面接触，从而增加导电元件与导电元件之间的接触面积 导电焊盘，从而加强导电元件和导电焊盘之间的接合，并防止导电元件与导电焊盘分层。
-
-
-
-
-
-
-
-
-
Search Results
29
records
(took 0.013 seconds)
