公开(公告)号：US09984892B2

公开(公告)日：2018-05-29

申请号：US15596060

申请日：2017-05-16

Applicant: Tokyo Electron Limited

Inventor： Takashi Kobayashi ,  Seishi Murakami ,  Takashi Sakuma ,  Masahiko Tomita ,  Takamichi Kikuchi ,  Akitaka Shimizu ,  Takayuki Kamaishi ,  Einosuke Tsuda

IPC: H01L21/302 ,  H01L21/308 ,  H01L21/285 ,  H01L21/67

CPC classification number: H01L21/3081 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67207

Abstract: Disclosed is a method for removing, from a target substrate having an insulating film with a predetermined pattern formed thereon, a silicon-containing oxide film formed in a silicon portion at a bottom of the pattern. The method includes: forming a carbon-based protective film on the entire surface of the insulating film including the pattern by ALD using a carbon source gas; selectively removing the carbon-based protective film on an upper surface of the insulating film and on the bottom of the pattern by an anisotropic plasma processing; removing the silicon-containing oxide film formed on the bottom of the pattern by etching; and removing a remaining portion of the carbon-based protective film.

公开(公告)号：US09425093B2

公开(公告)日：2016-08-23

申请号：US14561331

申请日：2014-12-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka ,  Takashi Sakuma ,  Osamu Yokoyama ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  C23C16/52 ,  C23C14/24 ,  C23C14/54 ,  C23C14/34

CPC classification number: C23C14/34 ,  C23C14/046 ,  C23C14/165 ,  C23C14/24 ,  C23C14/54 ,  C23C16/52 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate, includes: removing a tungsten oxide formed on a surface of the tungsten wiring; forming a nitriding preventing film at least on the surface of the tungsten wiring in the recess; forming a barrier film that prevents diffusion of Cu, on a surface in the recess from above the nitriding preventing film; forming a liner film on the barrier film; and filling a Cu film on the liner film.

Abstract translation: 通过将Cu填充到形成在基板中的凹部中，形成与钨布线接触而布置的Cu布线的Cu布线形成方法包括：去除形成在钨布线的表面上的氧化钨; 至少在所述凹部中的所述钨线的表面上形成防氮膜; 形成阻止膜从氮化防止膜上方阻止在凹部的表面上的扩散的阻挡膜; 在阻挡膜上形成衬垫膜; 并在衬膜上填充Cu膜。

公开(公告)号：US09253862B2

公开(公告)日：2016-02-02

申请号：US14044659

申请日：2013-10-02

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tatsuo Hirasawa ,  Osamu Yokoyama ,  Chiaki Yasumuro ,  Toshiaki Fujisato ,  Ryota Yoshida ,  Takashi Sakuma ,  Cheonsoo Han

IPC: H05H1/24 ,  H05F3/00 ,  C23C16/50 ,  C23C14/34 ,  C23C14/50 ,  H01J37/34 ,  H01L21/683 ,  H01J37/32

CPC classification number: H05F3/00 ,  C23C14/34 ,  C23C14/50 ,  C23C16/50 ,  H01J37/32568 ,  H01J37/34 ,  H01L21/6833

Abstract: In a plasma processing method, plasma processing is performed in a state where the object is attracted and held on the electrostatic chuck by applying a first voltage as an application voltage thereto and a thermal conduction gas is supplied to a gap between the electrostatic chuck and the object. The application voltage is decreased while stopping the supply of the thermal conduction gas and exhausting the thermal conduction gas remaining between the electrostatic chuck and the object upon completion of the plasma processing. The object is separated from the electrostatic chuck by setting the application voltage to the electrostatic chuck to zero after the application voltage is decreased.

Abstract translation: 在等离子体处理方法中，通过施加第一电压作为施加电压，将物体吸附并保持在静电卡盘上的状态下进行等离子体处理，并且向静电卡盘和静电卡盘之间的间隙供给导热气体 目的。 在等离子体处理完成时，施加电压降低，同时停止供给导热气体并排出残留在静电卡盘与物体之间的导热气体。 在施加电压降低之后，通过将静电卡盘的施加电压设定为零将物体与静电卡盘分离。

公开(公告)号：US20240363410A1

公开(公告)日：2024-10-31

申请号：US18620326

申请日：2024-03-28

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Yuji Otsuki ,  Kenichi Imakita ,  Atsushi Gomi ,  Kohichi Satoh ,  Tadahiro Ishizaka ,  Takashi Sakuma ,  Hidenao Suzuki

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76805

Abstract: A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.

公开(公告)号：US20180261464A1

公开(公告)日：2018-09-13

申请号：US15914071

申请日：2018-03-07

Applicant: Tokyo Electron Limited

Inventor： Takashi Kobayashi ,  Takashi Sakuma ,  Hideaki Yamasaki ,  Rio Shimizu ,  Einosuke Tsuda

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/67 ,  H01L21/285 ,  H01L21/677 ,  H01L29/45

Abstract: Disclosed is a method for removing, from a processing target substrate having an insulating film with a predetermined pattern formed thereon, a silicon-containing oxide film formed in a silicon portion of a bottom of the pattern. The method includes: removing the silicon-containing oxide film formed on the bottom of the pattern by ionic anisotropic plasma etching using plasma of a carbon-based gas; removing a remaining portion of the silicon-containing oxide film after the anisotropic plasma etching, by chemical etching; and removing a residue remaining after the chemical etching.

公开(公告)号：US09406557B2

公开(公告)日：2016-08-02

申请号：US14316251

申请日：2014-06-26

Applicant: TOKYO ELECTRON LIMITED

Inventor： Osamu Yokoyama ,  Cheonsoo Han ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Tatsuo Hirasawa ,  Tadahiro Ishizaka ,  Kenji Suzuki

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288

CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76876 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming a copper (Cu) wiring in a recess formed to have a predetermined pattern in an insulating film formed on a surface of a substrate. The method includes: forming a barrier film at least on a surface of the recess, the barrier film serving as a barrier for blocking diffusion of Cu; forming a Ru film on the barrier film by Chemical Mechanical Deposition (CVD); forming a Cu alloy film on the Ru film by Physical Vapor Deposition (PVD) to bury the recess; forming a Cu wiring using the Cu alloy film buried in the recess; and forming a dielectric film on the Cu wiring.

Abstract translation: 提供了在形成在基板表面上的绝缘膜中形成为具有预定图案的凹部中形成铜（Cu）布线的方法。 所述方法包括：至少在所述凹部的表面上形成阻挡膜，所述阻挡膜用作阻挡Cu的扩散的阻挡层; 通过化学机械沉积（CVD）在阻挡膜上形成Ru膜; 通过物理气相沉积（PVD）在Ru膜上形成Cu合金膜以埋藏凹槽; 使用埋在凹部中的Cu合金膜形成Cu布线; 并在Cu布线上形成电介质膜。

公开(公告)号：US09362166B2

公开(公告)日：2016-06-07

申请号：US14642331

申请日：2015-03-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka ,  Takashi Sakuma ,  Osamu Yokoyama ,  Kenji Matsumoto ,  Peng Chang ,  Hiroyuki Nagai

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed. The method includes: forming a manganese oxide film at least on a surface of the recess portion, the manganese oxide film serving as a self-aligned barrier film through reaction with the interlayer insulation layer; performing hydrogen radical treatment with respect to a surface of the manganese oxide film; placing a metal more active than ruthenium on the surface of the manganese oxide film after the hydrogen radical treatment; forming a ruthenium film on the surface where the metal more active than ruthenium is present; and forming a copper film on the ruthenium film by physical vapor deposition (PVD) to bury the copper film in the recess portion.

Abstract translation: 公开了一种埋设在衬底的层间绝缘层中形成的预定图案的凹部中的铜布线的形成方法。 该方法包括：通过与层间绝缘层反应，至少在凹部的表面上形成氧化锰膜，氧化锰膜作为自对准阻挡膜; 相对于氧化锰膜的表面进行氢自由基处理; 在氧自由基处理之后，将比钌更金属的氧化物膜置于氧化锰膜的表面上; 在其上存在比钌更有活性的金属的表面上形成钌膜; 并通过物理气相沉积（PVD）在钌膜上形成铜膜以将铜膜埋入凹部中。

公开(公告)号：US11993841B2

公开(公告)日：2024-05-28

申请号：US16996426

申请日：2020-08-18

Applicant: Tokyo Electron Limited

Inventor： Masato Araki ,  Kohichi Satoh ,  Tadahiro Ishizaka ,  Takashi Sakuma

IPC: C23C16/40 ,  C23C16/52

CPC classification number: C23C16/405 ,  C23C16/52

Abstract: There is provided a substrate processing method which includes placing a substrate on a stage provided inside a processing container, and forming a ruthenium film on the substrate, wherein forming the ruthenium film includes repeating a cycle including: supplying a ruthenium-containing gas and a CO gas into the processing container; and stopping the supply of the ruthenium-containing gas and the CO gas into the processing container and exhausting a gas within the processing container.

公开(公告)号：US11626290B2

公开(公告)日：2023-04-11

申请号：US17397561

申请日：2021-08-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Osamu Yokoyama ,  Kwangpyo Choi ,  Kazuki Hashimoto ,  Rio Shimizu ,  Takashi Kobayashi ,  Takashi Sakuma ,  Shinya Okabe

IPC: H01L21/311 ,  H01L21/67

Abstract: A method of etching silicon oxide on a surface of a substrate is provided. The method comprises alternately repeating heating the substrate to a heating temperature of 60° C. or higher, supplying hydrogen fluoride gas and ammonia gas onto the substrate to react with the silicon oxide, and modifying the silicon oxide to obtain a reaction product, and removing at least a portion of the reaction product from the substrate while stopping the supply of the above gases and continuing to heat the substrate at the heating temperature; and when a process gas that is at least one of the hydrogen fluoride gas and the ammonia gas is supplied, while continuing to supply the process gas from an upstream side of a flow path, closing a valve disposed in the flow path to pressurize the process gas in the flow path, and then opening the valve.

公开(公告)号：US09406558B2

公开(公告)日：2016-08-02

申请号：US14701555

申请日：2015-05-01

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka ,  Tatsuo Hirasawa ,  Takashi Sakuma ,  Osamu Yokoyama

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76882 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76883

Abstract: Cu wiring fabrication method for fabricating Cu wiring with respect to substrate having interlayer dielectric film having trench formed thereon, includes: forming barrier film on surface of the trench; forming Ru film on surface of the barrier film by CVD; burying the trench by forming Cu film or Cu alloy film on the Ru film; forming Cu film or Cu alloy film at corners of bottom of the trench while re-sputtering the formed Cu film or Cu alloy film in a condition where first formed Cu film or Cu alloy film re-sputtered by an ion action of the plasma generation gas; and subsequently burying the Cu film or the Cu alloy film in the trench in condition where the Cu film or the Cu alloy film is formed on field portion of the substrate, and reflows in the trench by an ion action of the plasma generation gas.

Abstract translation: 涉及在其上形成有沟槽的具有沟槽的层间绝缘膜的衬底制造Cu布线的Cu布线制造方法包括：在沟槽的表面上形成阻挡膜; 通过CVD在阻挡膜的表面上形成Ru膜; 通过在Ru膜上形成Cu膜或Cu合金膜来掩埋沟槽; 在沟槽底部的角落处形成Cu膜或Cu合金膜，同时在通过等离子体发生气体的离子作用重新溅射的第一次形成的Cu膜或Cu合金膜的条件下再溅射形成的Cu膜或Cu合金膜 ; 并且随后在衬底的场部形成Cu膜或Cu合金膜的状态下将Cu膜或Cu合金膜埋入沟槽中，并且通过等离子体产生气体的离子作用在沟槽中回流。