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1.发明授权Corrosion insensitive fusible link using capacitance sensing for semiconductor devices 失效使用半导体器件的电容感测的腐蚀不敏感的熔丝公开(公告)号：US06496053B1
公开(公告)日：2002-12-17
申请号：US09416977
申请日：1999-10-13
申请人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
发明人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.
摘要翻译： 用于编程设备或熔丝的结构和方法包括具有可改变的电容的电容电路。 电容电路可以包括第一电容器，连接到第一电容器的熔丝链和连接到熔丝链路的第二电容器，其中去除熔丝链的一部分改变电容。
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公开(公告)号：US20060099775A1
公开(公告)日：2006-05-11
申请号：US11317042
申请日：2005-12-22
申请人： Timothy Daubenspeck , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , William Motsiff , Mark Pouliot , Jennifer Robbins
发明人： Timothy Daubenspeck , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , William Motsiff , Mark Pouliot , Jennifer Robbins
IPC分类号： H01L21/78
CPC分类号： H01L23/585 , H01L21/31111 , H01L21/32134 , H01L21/76838 , H01L21/78 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
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公开(公告)号：US20080064189A1
公开(公告)日：2008-03-13
申请号：US11931194
申请日：2007-10-31
申请人： Timothy Daubenspeck , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , William Motsiff , Mark Pouliot , Jennifer Robbins
发明人： Timothy Daubenspeck , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , William Motsiff , Mark Pouliot , Jennifer Robbins
IPC分类号： H01L21/78
CPC分类号： H01L23/585 , H01L21/31111 , H01L21/32134 , H01L21/76838 , H01L21/78 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
摘要翻译： 使用在低K电介质材料中不形成诸如铜或银互连的自钝化氧化物层的金属互连形成在IC芯片上的集成电路（IC）的低K电介质材料的裂纹停止，以防止 在切割操作期间，由IC芯片的周边边缘形成的切屑和破裂引起的IC芯片的有源区的损坏。 形成作为沿着IC芯片的有效区域的外周边缘定位的金属堆叠的防潮层或边缘密封件。 裂纹停止部由位于IC芯片的外周上的防潮层/边缘密封件外部的至少一个沟槽或凹槽形成。
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公开(公告)号：US20080023833A1
公开(公告)日：2008-01-31
申请号：US11869787
申请日：2007-10-10
CPC分类号： H01L24/03 , H01L23/3171 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05023 , H01L2224/05073 , H01L2224/05124 , H01L2224/05558 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05671 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.
摘要翻译： 一种焊料凸块结构及其形成方法。 该结构包括（a）包括电介质层顶表面的电介质层（b）与电介质层顶表面直接物理接触的导电接合焊盘; （c）电介质层顶表面上的图案化支撑/界面层，并且在参考方向上比导电接合焊盘厚，其中图案化支撑/界面层包括孔和沟槽，其中孔直接位于电气 导电接合焊盘，并且其中所述沟槽不被任何导电材料填充; 和（d）填充该孔并电耦合到导电接合焊盘的导电焊料凸块。
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公开(公告)号：US20060267136A1
公开(公告)日：2006-11-30
申请号：US10908707
申请日：2005-05-24
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) chip with fused circuits and method of making the IC. Fuses in an upper wiring layer are formed using a multi-tone mask to define rounded bottom corners on the fuses, while wiring in the upper wiring layer maintain a rectangular cross-section.
摘要翻译： 具有融合电路的集成电路（IC）芯片和制造IC的方法。 使用多色调掩模形成上部布线层中的保险丝，以在熔丝上限定圆形的底角，而上部布线层中的布线保持矩形的横截面。
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公开(公告)号：US20060246703A1
公开(公告)日：2006-11-02
申请号：US10908084
申请日：2005-04-27
IPC分类号： H01L21/44
CPC分类号： H01L23/556 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05572 , H01L2224/13022 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/00 , H01L2924/00014
摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.
摘要翻译： 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。
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公开(公告)号：US20060057831A1
公开(公告)日：2006-03-16
申请号：US10711367
申请日：2004-09-14
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L2224/05001 , H01L2224/05073 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/05681 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014
摘要： A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.
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8.发明申请METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES 有权用于形成集成电路芯片和结果设备上的C4连接的方法公开(公告)号：US20070252274A1
公开(公告)日：2007-11-01
申请号：US11380215
申请日：2006-04-26
申请人： Timothy Daubenspeck , Mukta Farooq , Jeffrey Gambino , Christopher Muzzy , Kevin Petrarca , Wolfgang Sauter
发明人： Timothy Daubenspeck , Mukta Farooq , Jeffrey Gambino , Christopher Muzzy , Kevin Petrarca , Wolfgang Sauter
CPC分类号： H01L24/03 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/034 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05006 , H01L2224/05018 , H01L2224/05027 , H01L2224/05083 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/0517 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05556 , H01L2224/05559 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05671 , H01L2224/113 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/11901 , H01L2224/11902 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/13111 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/15788 , H01L2924/30107 , H01L2924/00014 , H01L2924/01007 , H01L2924/00015 , H01L2924/00011 , H01L2924/00012 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.
摘要翻译： 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。
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9.发明申请Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking 审中-公开用于可变厚度双镶嵌结构，其他灰度掩蔽工艺和使用灰色掩蔽制成的结构的单掩模工艺公开(公告)号：US20070212872A1
公开(公告)日：2007-09-13
申请号：US11748269
申请日：2007-05-14
IPC分类号： H01L21/4763 , H01L21/266
CPC分类号： H01L21/31144 , G03F1/50 , H01L21/3083 , H01L21/32139 , H01L21/76807 , H01L21/76808 , H01L21/76816 , H01L21/76885 , H01L2221/1021
摘要： By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be provided.
摘要翻译： 通过在半导体制造中使用具有至少两个灰度的多灰度蒙版掩模，现在可以在单一级别中进行多个布线厚度，其中先前只能提供一个布线厚度。 例如，可以提供单层中不同厚度的功率和信号线。
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公开(公告)号：US20070080455A1
公开(公告)日：2007-04-12
申请号：US11163235
申请日：2005-10-11
申请人： Donna Zupanski-Nielsen , William Landers , Ian Melville , Roger Quon , Timothy Daubenspeck , Kamalesh Srivastava , Mary Cullinan-Scholl , Lawrence Clevenger , Christopher Muzzy
发明人： Donna Zupanski-Nielsen , William Landers , Ian Melville , Roger Quon , Timothy Daubenspeck , Kamalesh Srivastava , Mary Cullinan-Scholl , Lawrence Clevenger , Christopher Muzzy
CPC分类号： H01L24/13 , H01L21/76831 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05647 , H01L2224/11334 , H01L2224/1148 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.
摘要翻译： 提供具有绝缘层，接触焊盘，通孔和牺牲电介质盖的半导体。 接触垫嵌入在绝缘层中，其中接触垫具有铜的顶部金属层。 通孔在顶部金属层上形成一个开口。 牺牲绝缘帽至少在顶部金属层之上。
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