公开(公告)号：US09761510B2

公开(公告)日：2017-09-12

申请号：US14706896

申请日：2015-05-07

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/488 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/488 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/12105 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48464 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2924/00

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

公开(公告)号：US09397138B2

公开(公告)日：2016-07-19

申请号：US14613231

申请日：2015-02-03

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to the carrier by a temporary bonding layer. The dam element is bonded on the wafer. A first isolation layer, a redistribution layer, a second isolation layer, and a conductive structure are formed on the wafer in sequence. The carrier, the dam element and the wafer are diced to form a semiconductor element. The semiconductor element is disposed on a printed circuit board, such that the conductive structure is electrically connected to the printed circuit board. An adhesion force of the temporary bonding layer is eliminated to remove the carrier. A lens assembly is disposed on the printed circuit board, such that the semiconductor element without the carrier is located in the lens assembly.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了载体和坝元件，并且坝元件通过临时粘合层粘附到载体上。 坝体结合在晶片上。 在晶片上依次形成第一隔离层，再分配层，第二隔离层和导电结构。 将载体，坝元件和晶片切割成半导体元件。 半导体元件设置在印刷电路板上，使得导电结构电连接到印刷电路板。 消除了临时粘合层的粘合力以除去载体。 透镜组件设置在印刷电路板上，使得没有载体的半导体元件位于透镜组件中。

公开(公告)号：US09379072B2

公开(公告)日：2016-06-28

申请号：US14552186

申请日：2014-11-24

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L31/00 ,  H01L23/00 ,  H01L25/00 ,  H01L27/146

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/8385 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14335 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract translation: 提供了包括第一基板的芯片封装。 多个第一导电焊盘设置在第一基板的第一侧上。 第二基板附接到与第一基板的第一侧相对的第二侧。 第二基板包括微电元件，并且具有多个与多个第一导电焊盘相对应的第二导电焊盘，该第二导电焊盘设置在第二基板的第一侧上且位于第一基板和第二基板之间。 再分配层设置在与第二基板的第一侧相对的第二侧上。 再分配层穿透第二基板，第二导电焊盘和第一基板并延伸到第一导电焊盘中以电连接第一和第二导电焊盘。

公开(公告)号：US10157811B2

公开(公告)日：2018-12-18

申请号：US15618054

申请日：2017-06-08

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  G06K9/00 ,  G01L19/14 ,  G06F21/32 ,  H01L21/02 ,  G01L19/00 ,  G01L19/06 ,  H01L23/525 ,  H01L21/60

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

公开(公告)号：US09935148B2

公开(公告)日：2018-04-03

申请号：US15181291

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US09771259B2

公开(公告)日：2017-09-26

申请号：US14932814

申请日：2015-11-04

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

公开(公告)号：US09543233B2

公开(公告)日：2017-01-10

申请号：US14869602

申请日：2015-09-29

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/52 ,  H01L23/00 ,  H01L23/528 ,  H01L21/683 ,  H01L21/768 ,  H01L21/268 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和与第一表面相对的第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面。 隔离层和导电垫在一起具有第二通孔，使得激光阻挡件通过第二通孔露出。 再分配层位于第三表面，第二通孔的侧壁和激光停止器上。

公开(公告)号：US09337115B2

公开(公告)日：2016-05-10

申请号：US14676671

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/02 ,  H01L21/56 ,  G01K1/00 ,  G06F21/32 ,  G06K9/00 ,  G01L19/06 ,  G01L19/14 ,  H01L21/60 ,  H01L23/525

CPC classification number: H01L23/3114 ,  G01K1/00 ,  G01L19/0627 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L2021/60022 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 基板包括感测装置和导电垫。 感测装置和导电垫与第一表面相邻。 导电垫具有从衬底的侧壁侧向突出的侧壁。 封装层附接到基板的第一表面以覆盖感测装置和导电垫。 再分配层设置在衬底的第二表面上并延伸以接触导电焊盘的侧壁。 再分布层的一端从衬底的第一表面突出并且与封装层的与第一表面相对的第三表面平齐。 还提供了一种形成芯片封装的方法。

公开(公告)号：US10056419B2

公开(公告)日：2018-08-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US09966358B2

公开(公告)日：2018-05-08

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/492 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.