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    Semiconductor Device and Method of Manufacture
    2.
    发明申请
    Semiconductor Device and Method of Manufacture 审中-公开

    公开(公告)号：US20190067179A1

    公开(公告)日：2019-02-28

    申请号：US16108535

    申请日：2018-08-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

    IPC分类号： H01L23/498 ,  H01L21/768

    摘要： A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the porous dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the porous dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

    THREE-STATE MEMORY DEVICE
    5.
    发明公开
    THREE-STATE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240365680A1

    公开(公告)日：2024-10-31

    申请号：US18764426

    申请日：2024-07-05

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Mauricio Manfrini

    IPC分类号： H10N50/80 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

    CPC分类号： H10N50/80 ,  H01L23/5226 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

    摘要： The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.

    BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FORMING THE SAME
    10.
    发明公开
    BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240363739A1

    公开(公告)日：2024-10-31

    申请号：US18770833

    申请日：2024-07-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chun-Tsung KUO ,  Chuan-Feng CHEN

    IPC分类号： H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC分类号： H01L29/732 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

    摘要： A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.