公开(公告)号：US12131764B2

公开(公告)日：2024-10-29

申请号：US18494278

申请日：2023-10-25

申请人： TOHOKU UNIVERSITY

发明人： Masanori Natsui ,  Daisuke Suzuki ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

IPC分类号： G11C11/16 ,  G06F17/14

CPC分类号： G11C11/1673 ,  G06F17/142 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1697

摘要： The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

公开(公告)号：US20240312505A1

公开(公告)日：2024-09-19

申请号：US18463418

申请日：2023-09-08

申请人： Kioxia Corporation

发明人： Naoki MATSUSHITA

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C11/1675 ,  G11C11/1697

摘要： According to one embodiment, a memory device includes a first memory cell, a second memory cell, a first interconnect connected to the first memory cell and the second memory cell, a second interconnect connected to the second memory cell, and a third circuit. The third circuit includes a first circuit connectable to the first interconnect and the second interconnect and a second circuit connectable to the first interconnect and the second interconnect. During a write operation or a read operation for the first memory cell, the first circuit outputs a first current to be supplied to the first memory cell, the second circuit outputs a third current based on a second current which flows through the second interconnect, and the third circuit supplies a sum of the first current and the third current to the first interconnect.

公开(公告)号：US20240130247A1

公开(公告)日：2024-04-18

申请号：US18397344

申请日：2023-12-27

申请人： TDK CORPORATION

发明人： Tomoyuki Sasaki

IPC分类号： H10N52/00 ,  G01R33/09 ,  G11B5/39 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC分类号： H10N52/00 ,  G01R33/098 ,  G11B5/39 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/18 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H03B15/006 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80 ,  H01F10/3286

摘要： This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

公开(公告)号：US11942131B2

公开(公告)日：2024-03-26

申请号：US17834074

申请日：2022-06-07

申请人： Samsung Electronics Co., Ltd.

发明人： Unghwan Pi

IPC分类号： G11C11/16 ,  G11C11/54

CPC分类号： G11C11/1673 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

摘要： A processing apparatus includes a bit-cell array including at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series, wherein each of the plurality of bit-cells includes: a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall; a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value; a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and a second switching element configured to switch an electrical signal applied to the second magnetic resistor.

公开(公告)号：US20240071452A1

公开(公告)日：2024-02-29

申请号：US18494278

申请日：2023-10-25

申请人： TOHOKU UNIVERSITY

发明人： Masanori Natsui ,  Daisuke Suzuki ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

IPC分类号： G11C11/16 ,  G06F17/14

CPC分类号： G11C11/1673 ,  G06F17/142 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1697

摘要： The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

公开(公告)号：US11900979B2

公开(公告)日：2024-02-13

申请号：US17508818

申请日：2021-10-22

申请人： INTEL CORPORATION

发明人： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

IPC分类号： G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

CPC分类号： G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

摘要： Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

公开(公告)号：US11830549B2

公开(公告)日：2023-11-28

申请号：US17855424

申请日：2022-06-30

申请人： SK hynix Inc. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

发明人： Tae Jung Ha ,  Soo Gil Kim ,  Jeong Hwan Song ,  Tae Joo Park ,  Tae Jun Seok ,  Hye Rim Kim ,  Hyun Seung Choi

IPC分类号： G11C13/00 ,  G11C11/16 ,  H10B63/00 ,  H10N70/00

CPC分类号： G11C13/0038 ,  G11C11/1697 ,  H10B63/20 ,  H10N70/841 ,  H10N70/8833

摘要： Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.

公开(公告)号：US11751375B2

公开(公告)日：2023-09-05

申请号：US17853206

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Ping-Wei Wang ,  Jui-Lin Chen ,  Yu-Kuan Lin

IPC分类号： G11C11/16 ,  H10B10/00 ,  G11C11/412 ,  H10B61/00 ,  H10N50/10

CPC分类号： H10B10/12 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1697 ,  G11C11/412 ,  H10B61/20 ,  H10N50/10

摘要： Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

公开(公告)号：US11688446B2

公开(公告)日：2023-06-27

申请号：US17846684

申请日：2022-06-22

申请人： SanDisk Technologies LLC

发明人： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L27/24

CPC分类号： G11C11/1659 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C11/1697 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L27/2481

摘要： Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

公开(公告)号：US20190051351A1

公开(公告)日：2019-02-14

申请号：US15936696

申请日：2018-03-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SUK-SOO PYO ,  Hyuntaek Jung ,  Taejoong Song

IPC分类号： G11C13/00 ,  G11C29/50

CPC分类号： G11C13/0028 ,  G11C5/147 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0054 ,  G11C2029/5006 ,  G11C2213/79 ,  G11C2213/82

摘要： A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells.