公开(公告)号：US06508878B2

公开(公告)日：2003-01-21

申请号：US09794615

申请日：2001-02-28

Applicant: Chin Kyo Kim ,  Tae Kyung Yoo

Inventor： Chin Kyo Kim ,  Tae Kyung Yoo

IPC: C30B2516

CPC classification number: C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007

Abstract: GaN system compound semiconductor and method for growing a crystal thereof, which can significantly reduce a concentration of crystalline defects caused by lattice mismatch by growing a GaN system compound semiconductor of GaN or InxGa1-xN by using InxAl1-xN crystal on a substrate as an intermediate buffer layer, the method including the steps of (1) providing a sapphire substrate, (2) growing an intermediate buffer layer of InxAl1-xN on the sapphire substrate, and (3) growing GaN or InxGa1-xN system compound semiconductor on the intermediate buffer layer.

Abstract translation: GaN系化合物半导体及其晶体生长方法，其可以通过在基板上使用In x Al 1-x N晶体作为中间体来生长GaN或In x Ga 1-x N的GaN系化合物半导体而显着降低由晶格失配引起的晶体缺陷的浓度 缓冲层，该方法包括以下步骤：（1）提供蓝宝石衬底，（2）在蓝宝石衬底上生长InxAl1-xN的中间缓冲层，以及（3）在中间层上生长GaN或In x Ga 1-x N系化合物半导体 缓冲层。

公开(公告)号：US06217651B1

公开(公告)日：2001-04-17

申请号：US09356319

申请日：1999-07-16

Applicant: Hisashi Kashino ,  Koichi Kanaya

Inventor： Hisashi Kashino ,  Koichi Kanaya

IPC: C30B2516

CPC classification number: C23C16/52 ,  C30B25/16

Abstract: In the process of thin film growth, actual temperature of a substrate is measured and corrected with low cost in short time. With first thin film growth equipment of which a difference between set temperature of a heating source and an actual temperature of the substrate (hereinafter, referred to as temperature characteristic) is known, a first calibration curve representing “thin film growth rate vs. substrate actual temperature” is prepared. Next, thin film growth is conducted at one set temperature T2 with use of second thin film growth equipment whose temperature characteristic is unknown, where a difference from a set temperature T1 reading from the first calibration curve in correspondence to a thin film growth rate G resulting from the thin film growth process is determined. This difference is added to a set temperature T3 in the diffusion controlled temperature region at which the thin film growth is actually performed, making it possible to achieve thin film growth at an accurate substrate surface temperature. The temperature characteristic of the first thin film growth equipment can be known based on a second calibration curve representing “sheet resistance vs. substrate actual temperature” prepared by using a test-use substrate by ion implantation.

Abstract translation: 在薄膜生长过程中，在短时间内以低成本测量和校正基板的实际温度。 利用第一薄膜生长设备，其中加热源的设定温度与基板的实际温度之间的差异（以下称为温度特性）是已知的，表示“薄膜生长速率对基板实际值”的第一校准曲线 温度“。 接下来，使用温度特性未知的第二薄膜生长设备在一个设定温度T2下进行薄膜生长，其中与从薄膜生长速率G相应的从第一校准曲线读取的设定温度T1的差异导致 从薄膜生长过程确定。 该差异被添加到实际进行薄膜生长的扩散控制温度区域的设定温度T3，使得可以在精确的基板表面温度下实现薄膜生长。 基于通过使用通过离子注入使用测试用基板制备的表示“薄层电阻与基板实际温度”的第二校准曲线，可以知道第一薄膜生长设备的温度特性。

公开(公告)号：US06190453B1

公开(公告)日：2001-02-20

申请号：US09353195

申请日：1999-07-14

Applicant: Mark R. Boydston ,  Gerald R. Dietze ,  Oleg V. Kononchuk

Inventor： Mark R. Boydston ,  Gerald R. Dietze ,  Oleg V. Kononchuk

IPC: C30B2516

CPC classification number: C30B29/06 ,  C30B25/18

Abstract: A method of growing epitaxial semiconductor layers with reduced crystallographic defects. The method includes growing a first epitaxial semiconductor layer on a semiconductor substrate under conditions of relatively high temperature and low source gas flow to heal defects in or on the surface of the substrate. Subsequently, a second epitaxial semiconductor layer is grown on the first layer under conditions of relatively low temperature and high source gas flow. The first epi layer acts as a low-defect seed layer by preventing defects in the surface of the substrate from propagating into the second epi layer. Optionally, a hydrogen chloride etch may be employed during a portion of the first epi layer growth to increase the efficacy of the first layer.

Abstract translation: 生长具有减少的晶体缺陷的外延半导体层的方法。 该方法包括在相对较高的温度和较低的源气流的条件下，在半导体衬底上生长第一外延半导体层，以在衬底的表面或表面上愈合缺陷。 随后，在相对较低的温度和较高的源气流的条件下，在第一层上生长第二外延半导体层。 通过防止衬底表面的缺陷传播到第二外延层中，第一外延层用作低缺陷种子层。 任选地，可以在第一外延层生长的一部分期间采用氯化氢蚀刻以增加第一层的功效。

公开(公告)号：US06521042B1

公开(公告)日：2003-02-18

申请号：US08667660

申请日：1996-06-21

Applicant: Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

Inventor： Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

IPC: C30B2516

CPC classification number: H01L29/882 ,  B82Y10/00 ,  B82Y15/00 ,  C30B23/002 ,  C30B29/40 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02631 ,  Y10T117/1004 ,  Y10T117/1008

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

Abstract translation: 基于过程模型，通过质谱仪（204）反馈信号生长层厚度控制（206）的分子束外延（202）。 实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。

公开(公告)号：US06428620B1

公开(公告)日：2002-08-06

申请号：US09680376

申请日：2000-10-05

Applicant: Kenji Yamagata ,  Kiyofumi Sakaguchi

Inventor： Kenji Yamagata ,  Kiyofumi Sakaguchi

IPC: C30B2516

CPC classification number: H01L21/0203 ,  C25D11/32 ,  H01L21/2007 ,  H01L21/76259 ,  Y10S438/96 ,  Y10S438/977

Abstract: An object of this invention is to provide a substrate processing method capable of satisfactorily performing in etching in the step of removing a porous silicon layer by etching. In order to achieve this object, a substrate processing method includes the anodizing step of forming a porous silicon layer on a major surface of a single-crystal silicon substrate, the silicon film formation step of growing a single-crystal silicon film on the porous silicon layer, the removal step of bonding a first substrate obtained by oxidizing a surface of the single-crystal silicon film to a second substrate as a supporting substrate, and removing a single-crystal silicon portion from a lower surface side of the first substrate to expose the porous silicon layer, and the etching step of etching the exposed porous silicon layer to remove the porous silicon layer on the single-crystal silicon film, wherein in washing after the anodizing step, a time in which the first substrate is removed from the electrolytic solution and exposed to the air until washing is limited to a range in which the porous silicon layer is prevented from remaining on the single-crystal silicon film in the etching step.

Abstract translation: 本发明的目的是提供一种在通过蚀刻去除多孔硅层的步骤中能够令人满意地进行蚀刻的基板处理方法。 为了实现该目的，基板处理方法包括在单晶硅基板的主表面上形成多孔硅层的阳极氧化步骤，在多孔硅上生长单晶硅膜的硅膜形成步骤 层，将通过将单晶硅膜的表面氧化的第一基板接合到作为支撑基板的第二基板的去除步骤，以及从第一基板的下表面侧去除单晶硅部分，以暴露 多孔硅层，以及蚀刻暴露的多孔硅层以去除单晶硅膜上的多孔硅层的蚀刻步骤，其中在阳极氧化步骤之后的洗涤中，将第一基底从电解液中除去的时间 溶液并暴露于空气中，直到洗涤被限制在其中防止多孔硅层残留在单晶硅膜上的范围内 蚀刻步骤。

公开(公告)号：US06409828B1

公开(公告)日：2002-06-25

申请号：US08526828

申请日：1995-09-12

Applicant: Tae S. Kim

Inventor： Tae S. Kim

IPC: C30B2516

CPC classification number: C30B25/02 ,  C23C16/455 ,  C23C16/52 ,  C30B25/14 ,  C30B29/40

Abstract: A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device (44) using a flow-flange reactor (10), by adjusting input flow ratios in the flow-flange (12) of the reactor (10). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor (10) are then adjusted in response to the first optimum set of input flow ratios.

Abstract translation: 公开了一种通过调节反应器（10）的流动凸缘（12）中的输入流量比来使用流动法兰反应器（10）在半导体器件（44）中实现所需厚度分布的方法和装置。 建立目标厚度剖面。 然后基于第一多个样品厚度分布和第一组多组样品输入流量比来响应于目标厚度分布来确定第一组最佳输入流量比，其中每个样品厚度分布对应于一个 的第一组多组样本输入流量比。 然后响应于第一最佳输入流量组而调节反应器（10）的输入流量比。

公开(公告)号：US06749687B1

公开(公告)日：2004-06-15

申请号：US09227679

申请日：1999-01-08

Applicant: Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

Inventor： Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

IPC: C30B2516

CPC classification number: C30B29/06 ,  C23C16/4405 ,  C23C16/481 ,  C30B25/02 ,  C30B25/105 ,  C30B25/14 ,  C30B33/005 ,  C30B33/02 ,  C30B33/12 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/66651

Abstract: A single-wafer, chemical vapor deposition reactor is provided with hydrogen and silicon source gas suitable for epitaxial silicon deposition, as well as a safe mixture of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the sane chamber. In particular, a sacrificial oxidation is performed, followed by a hydrogen bake to sublime the oxide and leave a clean substrate. Epitaxial deposition can follow in situ. A protective oxide can also be formed over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer can serve as the gate dielectric, and a polysilicon gate layer can be formed in situ over the oxide.

Abstract translation: 单晶片化学气相沉积反应器具有适用于外延硅沉积的氢和硅源气体，以及非反应性气体中的氧的安全混合物。 提供了在正常室内形成氧化物层和硅层的方法。 特别地，进行牺牲氧化，然后进行氢气烘烤以使氧化物升华并留下清洁的基材。 外延沉积可以原位追踪。 也可以在同一室内的外延层上形成保护性氧化物，防止关键外延层的污染。 或者，氧化物层可以用作栅极电介质，并且可以在氧化物上原位形成多晶硅栅极层。

公开(公告)号：US06726767B1

公开(公告)日：2004-04-27

申请号：US09763414

申请日：2001-02-22

Applicant: Alan D Marrs ,  Allister W. E. Dann ,  John L Glasper ,  Christopher Pickering ,  David J Robbins ,  John Russell

Inventor： Alan D Marrs ,  Allister W. E. Dann ,  John L Glasper ,  Christopher Pickering ,  David J Robbins ,  John Russell

IPC: C30B2516

CPC classification number: C30B25/16 ,  C23C16/52 ,  C30B25/186

Abstract: Layer processing to grow a layer structure upon a substrate surface comprises supplying a vapor mixture stream to the substrate (28) to deposit constituents, monitoring growth with an ellipsometer (12) and using its output in real-time growth control of successive pseudo-layers. A Bayesian algorithm is used to predict a probability density function for pseudo-layer growth parameters from initial surface composition, growth conditions and associated growth probabilities therewith, the function comprising discrete samples. Weights are assigned to the samples representing occurrence likelihoods based on most recent sensor output. A subset of the samples is chosen with selection likelihood weighted in favor of samples with greater weights. The subset provides a subsequent predicted probability density function and associated pseudo-layer growth parameters for growth control, and becomes a predicted probability density function for a further iteration of pseudo-layer growth.

Abstract translation: 在衬底表面上生长层结构的层处理包括将蒸汽混合物流供应到衬底（28）以沉积成分，利用椭偏仪监测生长（12），并使用其输出实现连续伪层的实时生长控制 。 贝叶斯算法用于预测来自初始表面组成，生长条件及其相关生长概率的伪层生长参数的概率密度函数，该函数包括离散样本。 根据最近的传感器输出，将重量分配给表示出现可能性的样本。 选择样本的子集，其中选择可能性加权，有利于具有更大权重的样本。 该子集提供用于生长控制的随后的预测概率密度函数和相关联的伪层生长参数，并且成为进一步迭代伪层生长的预测概率密度函数。

公开(公告)号：US06610141B2

公开(公告)日：2003-08-26

申请号：US10002790

申请日：2001-11-15

Applicant: Henry W. White ,  Shen Zhu ,  Yungryel Ryu

Inventor： Henry W. White ,  Shen Zhu ,  Yungryel Ryu

IPC: C30B2516

CPC classification number: H01L31/1836 ,  C23C14/081 ,  C23C14/086 ,  C23C14/28 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02395 ,  H01L21/02403 ,  H01L21/0242 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02587 ,  H01L21/02631 ,  H01L21/02661 ,  H01L21/2225 ,  H01L21/2255 ,  H01L29/22 ,  H01L29/267 ,  H01L29/7869 ,  H01L31/02963 ,  H01L33/0087 ,  H01L33/28 ,  H01L33/285 ,  H01S5/327 ,  Y02E10/50 ,  Y10T428/12681

Abstract: A p-type oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, a p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type oxide film has a net acceptor concentration of at least about 1015 acceptors/cm3, a resistivity of no greater than about 1 ohm-cm, and a Hall mobility of between about 0.1 and about 50 cm2/Vs.

公开(公告)号：US06336970B1

公开(公告)日：2002-01-08

申请号：US09415459

申请日：1999-10-14

Applicant: Ryo Sakamoto ,  Ryuichi Toba ,  Hiroyuki Ikeda

Inventor： Ryo Sakamoto ,  Ryuichi Toba ,  Hiroyuki Ikeda

IPC: C30B2516

CPC classification number: H01L21/02046 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02661

Abstract: A surface preparation method and semiconductor device constituted so as to enable the prevention of carrier accumulation resulting from Si acting as a donor, without making the constitution of a semiconductor manufacturing apparatus complex. When forming an epitaxial layer either on the surface of a substrate, or on the surface of a base layer, Si or an Si compound that exists on the surface of a substrate, or on the surface of a base layer, is removed in accordance with a thermal cleaning process that uses an As hydride gas as the cleaning gas.

Abstract translation: 一种表面制备方法和半导体器件，其构成为能够防止由作为供体的Si产生的载流子聚集，而不会使半导体制造装置的结构复杂化。 当在衬底的表面或基底层的表面上形成外延层时，根据存在于基底表面上或基底表面上的Si或Si化合物，根据 使用As氢化物气体作为清洁气体的热清洗方法。