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公开(公告)号：US12133392B2
公开(公告)日：2024-10-29
申请号：US17718071
申请日：2022-04-11
发明人： Meng-Han Lin , Chia-En Huang
CPC分类号： H10B51/30 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H10B51/20 , H01L29/66795 , H01L29/7855
摘要： A memory device comprises a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer is on a sidewall of the word line. The semiconductor layer is on a sidewall of the gate dielectric layer. The source line is in contact with a first region of a sidewall of the semiconductor layer. The resistance-switchable element is in contact with a second region of the sidewall of the semiconductor layer.
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2.发明公开公开(公告)号：US20240357829A1
公开(公告)日：2024-10-24
申请号：US18760062
申请日：2024-07-01
发明人： BO-FENG YOUNG , HAN-JONG CHIA , SAI-HOOI YEONG , YU-MING LIN , CHUNG-TE LIN
IPC分类号： H10B51/20 , H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L29/66 , H01L29/78 , H10B10/00 , H10B51/30 , H10B51/40
CPC分类号： H10B51/20 , H01L21/76898 , H01L21/8221 , H01L23/481 , H01L27/0688 , H01L29/66795 , H01L29/6684 , H01L29/78391 , H01L29/785 , H10B10/12 , H10B51/30 , H10B51/40
摘要： A semiconductor structure is provided. The semiconductor structure includes a first layer having a logic device; a lower second layer over the first layer; an upper second layer over the lower second layer; a first isolation layer sandwiching by the first layer and the lower second layer; and a plurality of though layer via structures (TLV) penetrating the lower second layer, the upper second layer, the first isolation layer, and the second isolation layer. The lower second layer has a lower memory device. The upper second layer has an upper memory device. A channel length of the upper memory device is longer than a channel length of the lower memory device.
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公开(公告)号：US20240357826A1
公开(公告)日：2024-10-24
申请号：US18757483
申请日：2024-06-27
发明人： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong , Han-Jong Chia
IPC分类号： H10B51/10 , H01L21/28 , H01L23/522 , H01L29/51 , H01L29/66 , H01L29/78 , H10B51/20 , H10B51/30
CPC分类号： H10B51/10 , H01L23/5226 , H01L29/40111 , H01L29/516 , H01L29/66666 , H01L29/78391 , H10B51/20 , H10B51/30
摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
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公开(公告)号：US20240349508A1
公开(公告)日：2024-10-17
申请号：US18751331
申请日：2024-06-23
摘要： A method of forming a device includes the following steps. A multi-layer stack is formed, wherein the multi-layer stack includes a plurality of dielectric layers and a plurality of first sacrificial layers stacked alternately. A first trench is formed in the multi-layer stack. A memory material layer is formed on a sidewall of the first trench. A channel layer is conformally on the sidewall of the first trench and over the memory material layer. A plurality of conductive pillars are formed in the first trench.
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公开(公告)号：US20240347397A1
公开(公告)日：2024-10-17
申请号：US18757370
申请日：2024-06-27
发明人： Sasikanth Manipatruni , Niloy Mukherjee , Noriyuki Sato , Tanay Gosavi , Mauricio Manfrini , Somilkumar J. Rathi , James David Clarkson , Rajeev Kumar Dokania , Debo Olaosebikan , Amrita Mathuriya
摘要： A method to deposit a multi-layer stack for device applications includes implementing a model driven target selection for deposition. One or more targets may be procured with an initial stoichiometric composition or elemental purity. The targets may be utilized to form the multi-layer stack, and measurements may be made of chemical composition and electrical properties of the multi-layer stack. The measurements may be compared to reference target values and if measurement results are not within tolerance, the composition of the targets can be changed to yield a successive multi-layer stack. The process can be iterated until measurement results are within tolerance of target results. Additional experimentation with post deposition thermal anneal can be performed to optimize multi-layer stack properties.
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公开(公告)号：US20240324239A1
公开(公告)日：2024-09-26
申请号：US18612011
申请日：2024-03-21
发明人： Daewon Ha , Kyunghwan Lee , Myunghun Woo
IPC分类号： H10B53/30 , G11C5/06 , H01L21/28 , H01L29/51 , H01L29/78 , H10B51/10 , H10B51/30 , H10B53/10
CPC分类号： H10B53/30 , G11C5/063 , H01L29/40111 , H01L29/516 , H01L29/78391 , H10B51/10 , H10B51/30 , H10B53/10
摘要： A semiconductor memory device includes a plurality of memory cells each including a first vertical channel transistor (VCT) and a second VCT arranged in a vertical direction and connected to each other in series, the plurality of memory cells respectively including a plurality of ferroelectric capacitors connected to the second VCT in parallel and arranged in the vertical direction, wherein the plurality of memory cells are arranged in columns and rows in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction.
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公开(公告)号：US12094971B2
公开(公告)日：2024-09-17
申请号：US18310022
申请日：2023-05-01
发明人： Yunseong Lee , Jinseong Heo , Sangwook Kim , Sanghyun Jo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/28 , H01L29/08 , H01L29/423 , H01L29/51 , H01L29/66 , H10B51/30
CPC分类号： H01L29/78391 , H01L21/02175 , H01L21/022 , H01L21/0228 , H01L29/0847 , H01L29/40111 , H01L29/42364 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/6684 , H01L21/02181 , H01L21/02189 , H10B51/30
摘要： An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
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公开(公告)号：US12089417B2
公开(公告)日：2024-09-10
申请号：US17459847
申请日：2021-08-27
发明人： Chia-En Huang , Meng-Han Lin
IPC分类号： H10B51/50 , H01L23/522 , H10B51/20 , H10B51/30
CPC分类号： H10B51/50 , H01L23/5226 , H10B51/20 , H10B51/30
摘要： Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.
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公开(公告)号：US12089415B2
公开(公告)日：2024-09-10
申请号：US17569988
申请日：2022-01-06
发明人： Yen-Chieh Huang , Hai-Ching Chen , Chung-Te Lin
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.
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公开(公告)号：US12069865B2
公开(公告)日：2024-08-20
申请号：US17567586
申请日：2022-01-03
发明人： Bo-Feng Young , Sai-Hooi Yeong , Chi On Chui , Yu-Ming Lin
IPC分类号： H01L51/30 , H01L21/02 , H01L21/768 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786 , H10B43/20 , H10B43/30 , H10B51/20 , H10B51/30 , H10B99/00
CPC分类号： H10B51/30 , H01L21/02565 , H01L21/02603 , H01L21/76816 , H01L21/76877 , H01L29/0673 , H01L29/24 , H01L29/42392 , H01L29/66969 , H01L29/78391 , H01L29/78696 , H10B43/20 , H10B43/30 , H10B51/20 , H10B99/00
摘要： 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.
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