METHODS FOR CONTACT CLEAN
    92.
    发明申请
    METHODS FOR CONTACT CLEAN 有权
    联系清洁方法

    公开(公告)号:US20120225558A1

    公开(公告)日:2012-09-06

    申请号:US13411398

    申请日:2012-03-02

    IPC分类号: H01L21/311 H01L21/3105

    摘要: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

    摘要翻译: 提供了从表面除去氧化物的方法和装置,所述表面包括硅和锗中的至少一种。 所述方法和装置特别适用于从接触结构的金属硅化物层去除天然氧化物。 该方法和装置有利地将蚀刻停止层蚀刻工艺和自然氧化物去除工艺集成在单个室中,从而在衬底转移过程期间消除自然氧化物生长或其它污染物再沉积。 此外,该方法和设备还提供了改进的三步化学反应过程,以有效地从金属硅化物层去除天然氧化物,而不会不利地改变接触结构的几何形状和形成在接触结构中的沟槽或通孔的临界尺寸 。

    PROCESS CHAMBER LID DESIGN WITH BUILT-IN PLASMA SOURCE FOR SHORT LIFETIME SPECIES
    93.
    发明申请
    PROCESS CHAMBER LID DESIGN WITH BUILT-IN PLASMA SOURCE FOR SHORT LIFETIME SPECIES 有权
    用于短期生物物种的内置等离子体源的过程室盖设计

    公开(公告)号:US20110265721A1

    公开(公告)日:2011-11-03

    申请号:US13095720

    申请日:2011-04-27

    IPC分类号: C23C16/00 B01J19/08

    摘要: An apparatus and a method for depositing materials, and more particularly a vapor deposition chamber configured to deposit a material during a plasma-enhanced process are provided. In one embodiment a chamber comprises a chamber body defining a process volume, a substrate support disposed in the process volume and configured to support one or more substrates, a process lid assembly disposed over the substrate support, wherein the process lid assembly has a plasma cavity configured to generate a plasma and provide one or more radical species to the process volume, a RF (radio frequency) power source coupled to the gas distribution assembly, a plasma forming gas source coupled with the process lid assembly, and a reactant gas source coupled with the process lid assembly.

    摘要翻译: 提供一种用于沉积材料的装置和方法,更具体地,提供了在等离子体增强过程期间配置成沉积材料的气相沉积室。 在一个实施例中,室包括限定处理体积的室主体,设置在处理容积中并被配置为支撑一个或多个基板的基板支撑件,设置在基板支撑件上方的过程盖组件,其中处理盖组件具有等离子体腔 被配置为产生等离子体并且为处理体积提供一个或多个自由基物质,耦合到气体分配组件的RF(射频)功率源,与处理盖组件耦合的等离子体形成气体源,以及反应气体源 与工艺盖组件。

    Integration sequences with top surface profile modification
    94.
    发明授权
    Integration sequences with top surface profile modification 失效
    具有顶面轮廓修改的积分序列

    公开(公告)号:US08043933B2

    公开(公告)日:2011-10-25

    申请号:US12620806

    申请日:2009-11-18

    IPC分类号: H01L21/76

    摘要: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.

    摘要翻译: 本发明的实施例一般涉及用于处理半导体衬底的装置和方法。 特别地,本发明的实施例涉及用于形成具有具有圆形底部的凹部的浅沟槽隔离的装置和方法。 本发明的一个实施例包括通过从填充的沟槽结构中去除一部分材料并且使凹部的圆角底部倒圆,在填充的沟槽结构中形成凹陷。 通过将填充在沟槽结构中的相同材料的共形层沉积在衬底上并且从凹部的侧壁去除材料的共形层来进行圆角底角。

    Tubular Holder
    95.
    发明申请
    Tubular Holder 审中-公开
    管状支架

    公开(公告)号:US20110250004A1

    公开(公告)日:2011-10-13

    申请号:US13081215

    申请日:2011-04-06

    申请人: Mei-Chang Chung

    发明人: Mei-Chang Chung

    IPC分类号: B43K23/016

    摘要: A tubular holder includes: a tubular wall defining a hollow space adapted to receive an object, and having axially opposite rear and front open ends, and a through hole extending through the tubular wall between the rear and front open ends; a clamp disposed at an outer side of the tubular wall and having a resilient claw extending into the hollow space through the through hole; and a push member disposed movably in the hollow space for pushing the object forward and having a stop face on an outer surface of the push member, the stop face being able to abut against a free end of the resilient claw to prevent rearward movement of the push member so that the push member can move only in a forward direction.

    摘要翻译: 管状夹持器包括:管状壁,其限定适于容纳物体的中空空间,并且具有轴向相对的后部和前部开口端;以及贯穿所述管状壁在所述后部和前部开口端之间延伸的通孔; 夹具,其设置在所述管状壁的外侧,并且具有通过所述通孔延伸到所述中空空间中的弹性爪; 以及推动构件,其可移动地设置在所述中空空间中,用于向前推动所述物体并且在所述推动构件的外表面上具有止动面,所述止动面能够抵靠所述弹性爪的自由端,以防止所述弹性爪的向后移动 推动构件,使得推动构件能够仅沿向前方向移动。

    Method and apparatus for trench and via profile modification
    96.
    发明授权
    Method and apparatus for trench and via profile modification 有权
    沟槽和通孔型材修改的方法和装置

    公开(公告)号:US07994002B2

    公开(公告)日:2011-08-09

    申请号:US12620799

    申请日:2009-11-18

    IPC分类号: H01L21/00

    摘要: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

    摘要翻译: 本发明的实施例一般涉及用于处理半导体衬底的装置和方法。 特别地,本发明的实施例涉及在填充沟槽和通孔之前进行沟槽和通孔轮廓修改的方法和装置。 本发明的一个实施例包括通过将沟槽结构暴露于蚀刻剂来形成牺牲层以压缩沟槽结构的顶部开口。 在一个实施方案中,蚀刻剂被配置为通过与第一材料反应并产生形成牺牲层的副产物来除去第一材料。

    NUCLEIC ACIDS ENCODING A HOUSE DUST MITE ALLERGEN, DER P III, AND USES THEREOF
    97.
    发明申请
    NUCLEIC ACIDS ENCODING A HOUSE DUST MITE ALLERGEN, DER P III, AND USES THEREOF 审中-公开
    核酸编码一个房屋尘土蛭石过敏原,第三阶段及其用途

    公开(公告)号:US20110059522A1

    公开(公告)日:2011-03-10

    申请号:US12358954

    申请日:2009-01-23

    IPC分类号: C12N5/0783 C07K16/18

    CPC分类号: C07K14/43531 A61K38/00

    摘要: Isolated nucleic acids encoding an allergen of Dermatophagoides pteronyssinus, Der p III, are disclosed. A cDNA encoding a peptide having a Der p III activity and a predicted molecular weight of about 24,985 daltons is also described. The nucleic acids can be used as probes to detect the presence of Der p III nucleic acid in a sample or for the recombinant production of peptides having an activity of Der p III. Peptides having an activity of Der p III can be used in compositions suitable for pharmaceutical administration or methods of diagnosing sensitivity to house dust mites.

    摘要翻译: 公开了编码Dermatophagoides pteronyssinus,Der p III的变应原的分离的核酸。 还描述了编码具有Der p III活性和约24,985道尔顿的预测分子量的肽的cDNA。 核酸可以用作探针,以检测样品中Der p III核酸的存在或重组产生具有Der p III活性的肽。 具有Der p III活性的肽可用于适用于药物施用的组合物或诊断对尘螨敏感性的方法。

    Inventory tracking mechanism for virtual wafer circuit probing subcontract
    98.
    发明授权
    Inventory tracking mechanism for virtual wafer circuit probing subcontract 有权
    虚拟晶圆电路探测分包的库存跟踪机制

    公开(公告)号:US07904351B2

    公开(公告)日:2011-03-08

    申请号:US10853913

    申请日:2004-05-26

    IPC分类号: G06Q10/00

    CPC分类号: G06Q10/087 G06Q20/203

    摘要: The present disclosure provides an inventory tracking method for use with semiconductor product. The method can be used to track wafer lots transferred from a front end such as a fabrication (fab) facility, to a back end such as a wafer circuit probe facility. The method includes tracking a lot of wafers being sent to the back end facility and receiving a status report from the back end facility. The status report is compared to a predetermined criteria, and the lot is designated as a first type, such as slow moving, if the status report fails to meet the predetermined criteria. A payment plan is then associated with the lot due to it being designated as slow moving.

    摘要翻译: 本公开提供了一种与半导体产品一起使用的库存跟踪方法。 该方法可以用于跟踪从诸如制造(fab)设备的前端传送的晶片批次到诸如晶片电路探针设备的后端。 该方法包括跟踪许多正在发送到后端设备的晶片并从后端设备接收状态报告。 将状态报告与预定标准进行比较,并且如果状态报告不能满足预定标准,则批次被指定为第一类型,例如缓慢移动。 然后由于被指定为缓慢移动,付款方案与批次相关联。

    INTEGRATION SEQUENCES WITH TOP SURFACE PROFILE MODIFICATION
    100.
    发明申请
    INTEGRATION SEQUENCES WITH TOP SURFACE PROFILE MODIFICATION 失效
    具有顶部表面轮廓修改的集成序列

    公开(公告)号:US20100129982A1

    公开(公告)日:2010-05-27

    申请号:US12620806

    申请日:2009-11-18

    IPC分类号: H01L21/28 H01L21/762

    摘要: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.

    摘要翻译: 本发明的实施例一般涉及用于处理半导体衬底的装置和方法。 特别地,本发明的实施例涉及用于形成具有具有圆形底部的凹部的浅沟槽隔离的装置和方法。 本发明的一个实施例包括通过从填充的沟槽结构中去除一部分材料并且使凹部的圆角底部倒圆,在填充的沟槽结构中形成凹陷。 通过将填充在沟槽结构中的相同材料的共形层沉积在衬底上并且从凹部的侧壁去除材料的共形层来进行圆角底角。