公开(公告)号：US09972495B1

公开(公告)日：2018-05-15

申请号：US15387984

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L21/28123 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66545

Abstract: Structures including one or more field-effect transistors and methods for forming a structure that includes one or more field-effect transistors. A first semiconductor fin and a second semiconductor fin are formed in which the second semiconductor fin is spaced from the first semiconductor fin. A semiconductor layer is formed that covers the first semiconductor fin and the second semiconductor fin. An opening is formed in the semiconductor layer that exposes the first semiconductor fin. A dielectric spacer is formed on at least one sidewall of the semiconductor layer bordering the opening.

公开(公告)号：US09916982B1

公开(公告)日：2018-03-13

申请号：US15383461

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang ,  John Zhang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L21/823437 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78

Abstract: Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.

公开(公告)号：US09870942B1

公开(公告)日：2018-01-16

申请号：US15410032

申请日：2017-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Ziyan Xu ,  Chengwen Pei

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/31155 ,  H01L23/5283

Abstract: A method includes providing a semiconductor structure having a silicon mandrel layer, a hardmask stack and a dielectric layer. A 1st portion and a 2nd portion of the mandrel layer are doped with a 1st concentration and a 2nd greater concentration of dopant respectively. 1st and 2nd mandrels are patterned into the 1st and 2nd portions of the mandrel layer respectively. The 1st and 2nd mandrels are oxidized in the same thermal oxidation process to form 1st oxidation spacers on sidewalls of the 1st mandrels and 2nd oxidation spacers on sidewalls of the 2nd mandrels. The 2nd oxidation spacers have a thickness that is greater than a thickness of the 1st oxidation spacers. The 1st and 2nd oxidation spacers are utilized to form 1st and 2nd metal lines respectively in the dielectric layer. The 1st and 2nd metal lines have a different thickness.

公开(公告)号：US09704971B2

公开(公告)日：2017-07-11

申请号：US14963397

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/786 ,  H01L29/78654

Abstract: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

公开(公告)号：US09576894B2

公开(公告)日：2017-02-21

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09548318B1

公开(公告)日：2017-01-17

申请号：US14936848

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Xusheng Wu

IPC: H01L21/3205 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/321 ,  H01L21/265 ,  H01L21/28 ,  H01L21/84 ,  H01L27/06 ,  H01L29/49 ,  H01L29/861

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32115 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6609 ,  H01L29/66545 ,  H01L29/861

Abstract: Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices are disclosed. Embodiments include providing a polysilicon dummy gate electrode between spacers and extending over a BP, an active area of a transistor, and a shallow-trench-isolation (STI) region therebetween; providing an interlayer dielectric surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work-function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate electrode; and planarizing the metal down to an upper surface of the spacers.

Abstract translation: 公开了通过基于FDSOI技术的装置中的RMG电极连接到背板（BP）或阱接触或二极管接头的方法。 实施例包括在间隔物之间​​提供多晶硅虚拟栅电极，并且在BP之间延伸，晶体管的有源区和它们之间的浅沟槽隔离（STI）区; 提供围绕所述间隔物和多晶硅虚拟栅电极的层间电介质; 去除多晶硅虚拟栅电极，在间隔物之间​​形成空腔; 在空腔中形成高k电介质层和功函数（WF）金属层; 去除暴露出BP的上表面的WF金属层，高k电介质层和STI区域的一部分; 用形成替代金属栅极的金属填充空腔; 并将金属平坦化到隔片的上表面。

公开(公告)号：US09490174B2

公开(公告)日：2016-11-08

申请号：US14279480

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jianwei Peng ,  Min-hwa Chi

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

Abstract translation: 提供了一种制造包括凸起接触结构的凸起鳍结构的方法。 该方法可以包括：提供底鳍结构; 提供至少一个辅助翅片结构，所述至少一个辅助翅片结构在所述基部翅片结构的一侧与所述底部翅片结构接触; 在基板结构上生长材料以形成凸起的翅片结构; 并且在所述至少一个辅助翅片结构上生长所述材料，其中所述至少一个辅助翅片结构接触所述基底翅片结构增加了在所述基底翅片结构与所述至少 一个辅助翅片结构形成凸起的接触结构。

公开(公告)号：US09419139B2

公开(公告)日：2016-08-16

申请号：US14560428

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Hongxiang Mo ,  Qi Zhang ,  Byoung-Gi Min ,  Jeasung Park

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/30604 ,  H01L21/823462 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack.

Abstract translation: 公开了在伪栅极去除期间使用氮化物来保护源极/漏极区域的方法以及所得到的器件。 实施例包括在基板上形成氧化物层; 在氧化物层上形成氮化物保护层; 在氮化物保护层上形成虚拟栅极层; 图案化在衬底的第一和第二部分上形成第一和第二虚拟栅极堆叠的氧化物，氮化物和伪栅极层，每个伪栅极堆叠包括伪栅极，氮化物保护层和氧化物层，其中一部分 氧化物层沿着衬底延伸超过虚拟栅极的侧边缘; 在第一和第二伪栅极堆叠的相对侧分别在衬底中形成第一和第二源极/漏极空腔; 分别在第一和第二源极/漏极腔中生长第一和第二eSiGe源极/漏极区域; 以及去除第一伪栅极和第二虚拟栅极堆叠。

公开(公告)号：US09419126B2

公开(公告)日：2016-08-16

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US09419015B1

公开(公告)日：2016-08-16

申请号：US14656758

申请日：2015-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78675

Abstract: Methods for integrating core and I/O components in IC devices utilizing a TFT I/O device formed on STI regions, and the resulting devices are disclosed. Embodiments include forming STI and FinFET regions in a Si substrate, the FinFET region having first and second adjacent sections; forming a nitride layer and a silicon layer, respectively, over the STI region and both sections of the FinFET region; removing a first section of the silicon and nitride layers through a mask to expose the first FinFET section; implanting the exposed FinFET section with a dopant; removing remaining sections of the mask; removing a second section of the silicon and nitride layers through a second mask to expose the second FinFET section; implanting the second FinFET section with another dopant; removing remaining sections of the second mask; and forming a TFT on the remaining silicon layer, wherein the TFT channel includes the silicon layer.

Abstract translation: 公开了利用在STI区域上形成的TFT I / O装置的集成电路装置中的核心和I / O部件的集成方法。 实施例包括在Si衬底中形成STI和FinFET区域，FinFET区域具有第一和第二相邻区段; 分别在STI区域和FinFET区域的两个部分上形成氮化物层和硅层; 通过掩模去除所述硅和氮化物层的第一部分以暴露所述第一FinFET部分; 用掺杂剂注入暴露的FinFET部分; 去除面罩的剩余部分; 通过第二掩模去除所述硅和氮化物层的第二部分以暴露所述第二FinFET部分; 用另一个掺杂剂注入第二FinFET部分; 去除所述第二掩模的剩余部分; 以及在剩余硅层上形成TFT，其中TFT沟道包括硅层。