公开(公告)号：US09318952B2

公开(公告)日：2016-04-19

申请号：US14180166

申请日：2014-02-13

Applicant: Intel Corporation

Inventor： Bradley S. Oraw ,  Telesphor Kamgaing

IPC: H02M3/07 ,  H02J1/10 ,  H02M1/00 ,  H02J9/00

CPC classification number: H02M3/07 ,  H02J1/102 ,  H02J9/005 ,  H02M2001/008 ,  Y10T307/406

Abstract: Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.

Abstract translation: 串联交换机供电。 作为电流源工作的调节器与开关电容分压器并联布置。 开关电容器分配器与多个线性调节器串联配置，每个线性调节器调节来自开关电容器分压器的多个电压输出中的一个。 在另一个实施例中，串联开关桥具有跨越电压输入与第二对开关串联连接的第一对开关，一对开关内的每个开关与另一个开关同相切换，而第一对开关为 与第二对开关切换异相。 平衡电容器耦合在第一对和第二对中的一个开关上，以在两对开关中的任一个闭合时并联，以减少开关之间的电荷不平衡。

公开(公告)号：US12183961B2

公开(公告)日：2024-12-31

申请号：US17403571

申请日：2021-08-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/16 ,  H01P3/12 ,  H01P11/00 ,  H01Q9/04 ,  H04L67/10

Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.

公开(公告)号：US20240363556A1

公开(公告)日：2024-10-31

申请号：US18139204

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/50 ,  H01Q9/04

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01Q1/50 ,  H01Q9/0457 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08147 ,  H01L2224/08267 ,  H01L2224/16267 ,  H01L2224/2929 ,  H01L2224/29499 ,  H01L2224/32267 ,  H01L2224/32268

Abstract: An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US12107314B2

公开(公告)日：2024-10-01

申请号：US16911934

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Henning Braunisch ,  Diego Correas-Serrano

IPC: H01P5/02 ,  H01P1/04 ,  H01P1/20 ,  H01P3/00 ,  H01P3/16 ,  H01Q5/328 ,  H01Q13/26

CPC classification number: H01P5/028 ,  H01P1/047 ,  H01P1/2002 ,  H01P3/003 ,  H01P3/16 ,  H01Q5/328 ,  H01Q13/26

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US20240234234A9

公开(公告)日：2024-07-11

申请号：US17972923

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20240136279A1

公开(公告)日：2024-04-25

申请号：US17972975

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20240136243A1

公开(公告)日：2024-04-25

申请号：US17972923

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US11887946B2

公开(公告)日：2024-01-30

申请号：US17958300

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Adel A. Elsherbini ,  Sasha N. Oster

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/36 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q9/30

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01Q1/36 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q9/30

Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

公开(公告)号：US20230395456A1

公开(公告)日：2023-12-07

申请号：US17831100

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Jean-Pierre Njante ,  Telesphor Kamgaing

IPC: H01L23/367 ,  H01L23/528 ,  H01L23/373

CPC classification number: H01L23/3672 ,  H01L23/3738 ,  H01L23/5283

Abstract: Thermally conductive, electrically insulating materials and their manufacture on integrated circuit (IC) dies. An IC die may include a substrate with transistors on one side and, on the first and/or a second side, electrically insulating materials enhanced with thermally conductive materials. Such an IC die may be included in a system with a power supply. Such materials may be co-deposited, or interspersed, or interleaved together in a composite material.

公开(公告)号：US11830787B2

公开(公告)日：2023-11-28

申请号：US16532956

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/38 ,  H01L25/18 ,  H01L23/00 ,  H03H9/205 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/427 ,  H03H9/05 ,  H03H9/02 ,  H01L23/498 ,  H10N10/17 ,  H10N30/88 ,  H10N39/00 ,  H01L23/552

CPC classification number: H01L23/38 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/18 ,  H03H9/02102 ,  H03H9/0514 ,  H03H9/205 ,  H10N10/17 ,  H10N30/883 ,  H10N39/00 ,  H01L23/552 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2223/6644 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/3025 ,  H01L2924/30111

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.