公开(公告)号：US10312237B2

公开(公告)日：2019-06-04

申请号：US16058173

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/06 ,  H01L27/24 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：US10297598B2

公开(公告)日：2019-05-21

申请号：US15406985

申请日：2017-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul Jamison ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US10242919B2

公开(公告)日：2019-03-26

申请号：US15963566

申请日：2018-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Choonghyun Lee ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：US10157923B2

公开(公告)日：2018-12-18

申请号：US15806759

申请日：2017-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8228 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/24 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：US20180358269A1

公开(公告)日：2018-12-13

申请号：US15963566

申请日：2018-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Choonghyun Lee ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：US20180350811A1

公开(公告)日：2018-12-06

申请号：US16058173

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/82285 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L27/2454 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/78642

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：US20180240865A1

公开(公告)日：2018-08-23

申请号：US15788421

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/0607 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/321 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.

公开(公告)号：US20180076040A1

公开(公告)日：2018-03-15

申请号：US15262206

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L21/28255 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L29/161 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US12156395B2

公开(公告)日：2024-11-26

申请号：US17644076

申请日：2021-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Alexander Reznicek

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

公开(公告)号：US11881505B2

公开(公告)日：2024-01-23

申请号：US17198214

申请日：2021-03-10

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Xin Miao ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.