公开(公告)号：US20240105798A1

公开(公告)日：2024-03-28

申请号：US17935652

申请日：2022-09-27

申请人： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Elliot Tan ,  Shem Ogadhoh ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Wilfred Gomes

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Elliot Tan ,  Shem Ogadhoh ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Wilfred Gomes

IPC分类号： H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

摘要： An example IC device formed using trim patterning as described herein may include a support structure, a first elongated structure (e.g., a first fin or nanoribbon) and a second elongated structure (e.g., a second fin or nanoribbon), proximate to an end of the first elongated structure. An angle between a projection of the first elongated structure on the support structure and an edge of the support structure may be between about 5 and 45 degrees, while an angle between a projection of the second elongated structure on the support structure and the edge of the support structure may be less than about 15 degrees.

公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

申请人： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

发明人： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

摘要： Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US09716037B2

公开(公告)日：2017-07-25

申请号：US13995678

申请日：2011-12-22

申请人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

发明人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC分类号： H01L21/768 ,  H01L27/088 ,  H01L21/306 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US09608059B2

公开(公告)日：2017-03-28

申请号：US13995418

申请日：2011-12-20

申请人： Annalisa Cappellani ,  Stephen M. Cea ,  Tahir Ghani ,  Harry Gomez ,  Jack T. Kavalieros ,  Patrick H. Keys ,  Seiyon Kim ,  Kelin J. Kuhn ,  Aaron D. Lilak ,  Rafael Rios ,  Mayank Sahni

发明人： Annalisa Cappellani ,  Stephen M. Cea ,  Tahir Ghani ,  Harry Gomez ,  Jack T. Kavalieros ,  Patrick H. Keys ,  Seiyon Kim ,  Kelin J. Kuhn ,  Aaron D. Lilak ,  Rafael Rios ,  Mayank Sahni

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/775 ,  H01L27/12 ,  B82Y10/00

CPC分类号： H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US09461143B2

公开(公告)日：2016-10-04

申请号：US13622974

申请日：2012-09-19

申请人： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

发明人： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/785

摘要： Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

摘要翻译： 描述了设置在门的有效部分上的栅极接触结构以及形成这种栅极接触结构的方法。 例如，半导体结构包括具有有源区和隔离区的衬底。 栅极结构具有设置在有源区上方的部分和设置在衬底的隔离区上方的部分。 源极和漏极区域设置在衬底的有源区域中，位于栅极结构的位于有源区域之上的部分的任一侧上。 栅极接触结构设置在栅极结构的设置在衬底的有源区上方的部分上。

公开(公告)号：US09224810B2

公开(公告)日：2015-12-29

申请号：US13996503

申请日：2011-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且在离散通道区域的任一侧上包括离散通道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US09117791B2

公开(公告)日：2015-08-25

申请号：US13990238

申请日：2011-09-30

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L31/00 ,  H01L21/02 ,  H01L29/36 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。 根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层以显着降低接触电阻。 根据本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非限制的通道结构，许多晶体管配置和合适的制造工艺将是显而易见的。 分级缓冲可用于减少错配错位。 这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

公开(公告)号：US09048260B2

公开(公告)日：2015-06-02

申请号：US13997161

申请日：2011-12-31

申请人： Ritesh Jhaveri ,  Bernard Sell ,  Tahir Ghani

发明人： Ritesh Jhaveri ,  Bernard Sell ,  Tahir Ghani

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

摘要： A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

摘要翻译： 在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度，并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

公开(公告)号：US09029221B2

公开(公告)日：2015-05-12

申请号：US13995467

申请日：2011-12-21

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Aura Cecilia Davila Latorre ,  Tahir Ghani

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Aura Cecilia Davila Latorre ,  Tahir Ghani

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L21/308

CPC分类号： H01L29/7831 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66484

摘要： Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different.

摘要翻译： 描述具有调制高度的三维体的半导体器件和形成这种器件的方法。 例如，半导体结构包括具有设置在基板上方的第一半导体本体的第一半导体器件。 第一半导体本体具有第一高度和具有第一水平面的最上表面。 半导体结构还包括具有设置在衬底上方的第二半导体本体的第二半导体器件。 第二半导体本体具有第二高度和具有第二水平面的最上表面。 第一和第二水平面是共面的，第一和第二高度是不同的。

公开(公告)号：US20140197377A1

公开(公告)日：2014-07-17

申请号：US13996503

申请日：2011-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。