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    SYSTEMS AND METHODS FOR PROVIDING MEMORY MODULES WITH MULTIPLE HUB DEVICES
    92.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING MEMORY MODULES WITH MULTIPLE HUB DEVICES 有权
    用多个集线器件提供存储器模块的系统和方法

    公开(公告)号：US20070276977A1

    公开(公告)日：2007-11-29

    申请号：US11420046

    申请日：2006-05-24

    申请人： Paul W. Coteus ,  Warren E. Maule ,  Edward J. Seminaro ,  Robert B. Tremaine

    发明人： Paul W. Coteus ,  Warren E. Maule ,  Edward J. Seminaro ,  Robert B. Tremaine

    IPC分类号： G06F13/14 ,  G06F12/00

    CPC分类号： G06F13/4243 ,  G06F13/4247

    摘要： Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.

    摘要翻译： 为多个集线器设备提供内存模块的系统和方法。 示例性系统包括具有存储器总线的级联互连存储器系统，存储器控制器和存储器模块。 存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。 存储器模块包括具有三个或更多个端口的第一集线器设备和具有三个或更多个端口的第二集线器设备。 第一集线器设备上的第一端口经由存储器总线与存储器控制器通信，第一集线器设备上的第二端口与第一组存储器设备通信，第一集线器设备上的第三端口级联 连接到第二集线器设备上的第一端口。 第二集线器设备上的第二端口与第二组存储器设备通信，并且第二集线器设备上的第三端口支持与存储器系统中的后续集线器设备的级联连接。

    High density, high performance memory circuit package
    93.
    发明授权
    High density, high performance memory circuit package 失效
    高密度，高性能存储电路封装

    公开(公告)号：US5421079A

    公开(公告)日：1995-06-06

    申请号：US148970

    申请日：1993-11-08

    申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Alphonso P. Lanzetta

    发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Alphonso P. Lanzetta

    IPC分类号： H01L25/10 ,  H05K3/30 ,  H05K7/02 ,  B23P19/04

    CPC分类号： H05K7/023 ,  H01L25/105 ,  H05K3/301 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  Y10T29/53265

    摘要： A high density circuit package includes a pair of planar packages, the planar packages exhibiting front and back surfaces and positioned back-to-back in the high density circuit package. Each planar package includes a flexible circuit carrier having a plurality of circuit chips mounted thereon. Front and back planar metallic heat sinks sandwich the circuit carriers, at least one of the heat sinks contacting a surface of the chips mounted on the sandwiched circuit carriers. Each heat sink is provided with air flow apertures formed in its planar surface and adjacent to each circuit chip. A circuit card interconnects with the circuit carriers in an interconnection region and is pluggable into a female connector. The planar metallic heat sinks and circuit carriers are mechanically packaged so as to provide a planar arrangement which aligns the apertures in both the front and rear heat sinks. A pair of planar packages are mechanically connected in a back-to-back arrangement so that the apertures therebetween are aligned. The associated circuit cards are also back-to-back oriented so as to enable their joint interconnection into the female connector.

    摘要翻译： 高密度电路封装包括一对平面封装，平面封装呈现前后表面并且背对背设置在高密度电路封装中。 每个平面封装包括具有安装在其上的多个电路芯片的柔性电路载体。 前后平面金属散热器夹着电路载体，至少一个散热片接触安装在夹层电路载体上的芯片表面。 每个散热器设置有形成在其平面表面中并与每个电路芯片相邻的气流孔。 电路卡与互连区域中的电路载体互连，并且可插入到母连接器中。 平面金属散热器和电路载体被机械地封装，以便提供一个平面布置，其对准前后散热片中的孔。 一对平面封装以背对背布置机械连接，使得它们之间的孔对准。 相关联的电路卡也是背靠背定向的，以便使它们的连接互连到母连接器中。

    Wiring topology for transfer of electrical signals
    94.
    发明授权
    Wiring topology for transfer of electrical signals 失效
    用于传输电信号的接线拓扑

    公开(公告)号：US5394121A

    公开(公告)日：1995-02-28

    申请号：US137529

    申请日：1993-10-15

    申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  William R. Hardell, Jr.

    发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  William R. Hardell, Jr.

    IPC分类号： G11C7/10 ,  H01P5/12

    CPC分类号： G11C7/1048

    摘要： Wiring topology and hierarchy of transmission line impedances for connecting I/O of semiconductor devices together. This arrangement gives smooth signal shapes for signal rise and fall times as fast as one (1) nsec or faster. The design uses a balanced multi-way branched net with increasing impedance until very close to the end, of the net, where it is a balanced multi-way branched net with unterminated ends. Thus, coming out of the signal driver is a single impedance transmission line. This single impedance transmission line (A) then branches into two impedance transmission lines (B), each having an impedance higher than the single line impedance that feeds it. These lines (B) are used to drive electronic modules. After entering the electronic modules through a connector, each of these lines (B) then branch into two transmission lines (C) having a yet higher impedance value. Each of these lines (C) finally ends in a cluster of four transmission lines (D. Each of these final lines (D) connects to electronic devices on the electronic module.

    摘要翻译： 用于将半导体器件的I / O连接在一起的传输线阻抗的布线拓扑和层次结构。 这种布置为信号上升和下降时间提供平滑的信号形状，速度可达一（1）nsec或更快。 该设计使用一个平衡的多路分支网络，其阻抗增加到非常接近网络的末端，在那里它是一个平衡的多路分支网络，没有终端。 因此，从信号驱动器出来的是单阻抗传输线。 该单阻抗传输线（A）然后分支成两个阻抗传输线（B），每条阻抗传输线具有高于馈送它的单线路阻抗的阻抗。 这些线（B）用于驱动电子模块。 在通过连接器进入电子模块之后，这些线（B）中的每一条然后分支成具有更高阻抗值的两条传输线（C）。 这些线（C）中的每一条最终终止于四条传输线的群集（D.这些最后一行（D）中的每一行连接到电子模块上的电子设备。

    Packages for stacked integrated circuit chip cubes
    95.
    发明授权
    Packages for stacked integrated circuit chip cubes 失效
    堆叠集成电路芯片立方体的封装

    公开(公告)号：US5343366A

    公开(公告)日：1994-08-30

    申请号：US903838

    申请日：1992-06-24

    申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

    发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

    IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H01R23/68

    CPC分类号： H05K3/363 ,  H01L24/01 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06596 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09172 ,  H05K2201/09909 ,  H05K2201/10484 ,  H05K2201/1059 ,  H05K2201/10681 ,  H05K2201/10984 ,  H05K3/326 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/366 ,  H05K3/4007 ,  H05K3/4092

    摘要： This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.

    摘要翻译： 本发明涉及将集成电路芯片三维封装成堆栈以形成立方体结构。 在堆叠中的相邻芯片之间，设置有电互连装置，其是具有多个导体的第一基板，其多个导体电连接到芯片接触位置，并且其另一端延伸到芯片堆叠的一侧， 形成多个针状电互连组件。 销状结构可以由在其至少一侧上具有电导体的第一基板的凸起从该侧延伸形成。 或者，销状结构可以由从第一基板的边缘的两侧悬臂的导体形成，并且其中来自两侧的相应导体对准并且间隔开第一基板厚度。 这些空间包含焊料并形成焊料加载的针状结构。 销状结构可以直接焊接到第二衬底表面上的导体上，或者针状结构可以适于插入到第二衬底中的孔中。 第二基板提供用于电连接多个这些长方体的装置。 优选地，第一和第二基底是电路化柔性聚合物膜。 第二基板设置在诸如PC板的第三基板上，其间具有弹性材料，其允许将散热器压紧成与长方体结构的相对侧紧密接触。

    T-star interconnection network topology
    99.
    发明授权
    T-star interconnection network topology 有权
    T星互连网络拓扑

    公开(公告)号：US09077616B2

    公开(公告)日：2015-07-07

    申请号：US13569789

    申请日：2012-08-08

    申请人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    发明人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    IPC分类号： H04L12/24 ,  H04L12/715

    CPC分类号： H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

    摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.

    摘要翻译： 根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括 路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。 此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

    T-STAR INTERCONNECTION NETWORK TOPOLOGY
    100.
    发明申请
    T-STAR INTERCONNECTION NETWORK TOPOLOGY 有权
    T-STAR互联网络拓扑

    公开(公告)号：US20140044006A1

    公开(公告)日：2014-02-13

    申请号：US13569789

    申请日：2012-08-08

    申请人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    发明人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    IPC分类号： H04L12/28

    CPC分类号： H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

    摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.

    摘要翻译： 根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括 路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。 此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。