公开(公告)号：US20190311756A1

公开(公告)日：2019-10-10

申请号：US16432250

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Ankit Sharma ,  Haitao Liu ,  Albert Fayrushin ,  Akira Goda ,  Kamal M. Karda

IPC: G11C11/22 ,  H01L27/105 ,  H01L27/11502

Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.

公开(公告)号：US20190206870A1

公开(公告)日：2019-07-04

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/423

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

公开(公告)号：US10153299B2

公开(公告)日：2018-12-11

申请号：US15398303

申请日：2017-01-04

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11585 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11514 ,  G11C11/22

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US20180323214A1

公开(公告)日：2018-11-08

申请号：US16020712

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L29/49 ,  H01L27/11585 ,  H01L21/28 ,  H01L29/51 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/11582

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US20170373247A1

公开(公告)日：2017-12-28

申请号：US15684081

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L43/10 ,  H01L23/535

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

公开(公告)号：US20170236828A1

公开(公告)日：2017-08-17

申请号：US15584371

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/11502 ,  H01L27/108 ,  H01L27/11507 ,  H01L49/02 ,  H01G4/08

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US09673203B2

公开(公告)日：2017-06-06

申请号：US15064988

申请日：2016-03-09

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/00 ,  H01L27/11502 ,  H01L27/11507 ,  H01L49/02

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US20160240545A1

公开(公告)日：2016-08-18

申请号：US15064988

申请日：2016-03-09

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Abstract translation: 存储单元包括与选择装置串联电耦合的选择装置和电容器。 该电容器包括两个导电电容器电极，其间具有铁电材料。 该电容器具有从电容器电极中的一个通过铁电材料到另一个的本征电流泄漏路径。 存在从一个电容器电极到另一个电容器电极的平行电流泄漏路径。 并联电流泄漏路径与固有路径电路并联，总内阻小于固有路径。 公开其他方面。

公开(公告)号：US20160141336A1

公开(公告)日：2016-05-19

申请号：US15004744

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/786

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

公开(公告)号：US20150200308A1

公开(公告)日：2015-07-16

申请号：US14519021

申请日：2014-10-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。