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    Integrating through substrate vias from wafer backside layers of integrated circuits
    91.
    发明授权
    Integrating through substrate vias from wafer backside layers of integrated circuits 有权
    通过集成电路的晶片背面层的衬底通孔进行积分

    公开(公告)号：US09219032B2

    公开(公告)日：2015-12-22

    申请号：US13790625

    申请日：2013-03-08

    Applicant: QUALCOMM Incorporated

    Inventor： Vidhya Ramachandran ,  Shiqun Gu

    IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/49827 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13024

    Abstract: A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

    Abstract translation: 半导体晶片具有从半导体晶片的背面形成的集成通孔基板通孔。 半导体晶片包括在半导体衬底的表面上的半导体衬底和浅沟槽隔离（STI）层焊盘。 半导体晶片还包括形成在接触蚀刻停止层上的层间介电层（ILD）层，将ILD层与半导体衬底的表面上的STI层焊盘分离。 半导体晶片还包括穿过STI层焊盘和半导体衬底延伸穿过衬底通孔，以与ILD层内的至少一个触点耦合。 贯通基板通孔包括导电填充材料和侧壁隔离衬层。 侧壁隔离衬垫层具有可能延伸到但不穿过STI层衬垫的部分。

    Integrated circuit module with lead frame micro-needles
    92.
    发明授权
    Integrated circuit module with lead frame micro-needles 有权
    集成电路模块，带引线框微针

    公开(公告)号：US09202705B1

    公开(公告)日：2015-12-01

    申请号：US14824345

    申请日：2015-08-12

    Applicant: QUALCOMM Incorporated

    Inventor： Kenneth Kaskoun ,  Rongtian Zhang ,  Matthew Michael Nowak ,  Shiqun Gu

    IPC: H01L21/44 ,  H01L21/48 ,  H01L21/306 ,  H01L23/495

    CPC classification number: H01L21/306 ,  A61B5/04 ,  A61B5/685 ,  A61B2562/12 ,  A61M37/0015 ,  A61M2037/0023 ,  A61M2037/0053 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/49548 ,  H01L2224/16225

    Abstract: An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.

    Abstract translation: 描述了具有用于医疗装置的引线框微针的集成电路（IC）模块以及形成IC模块的方法。 所述方法包括形成包括一体地形成在其中的微针的引线框架坯料。 微针可以弯曲超过引线框架坯件的初始下侧。 初始下侧可以与保护层接合，使得弯曲的微针嵌入保护层中，保护层可以可拆卸地附接到初始下侧和弯曲的微针。 IC部件可以固定在引线框架坯料的上侧。 引线框架坯料的IC部件和芯的上表面可以用形成IC模块封装的模塑料封装。 去除保护层可能使弯曲的微针暴露在远离包装的位置。

    INTEGRATED DEVICE COMPRISING HIGH DENSITY INTERCONNECTS AND REDISTRIBUTION LAYERS
    95.
    发明申请
    INTEGRATED DEVICE COMPRISING HIGH DENSITY INTERCONNECTS AND REDISTRIBUTION LAYERS 有权
    包含高密度互连和重新分配层的集成设备

    公开(公告)号：US20150255416A1

    公开(公告)日：2015-09-10

    申请号：US14196817

    申请日：2014-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

    IPC: H01L23/00 ,  H01L23/31

    CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

    Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

    Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

    Integrating through substrate vias into middle-of-line layers of integrated circuits
    99.
    发明授权
    Integrating through substrate vias into middle-of-line layers of integrated circuits 有权
    通过衬底通孔集成到集成电路的中间线层

    公开(公告)号：US08975729B2

    公开(公告)日：2015-03-10

    申请号：US13724038

    申请日：2012-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Vidhya Ramachandran ,  Shiqun Gu

    IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

    CPC classification number: H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.

    Abstract translation: 半导体晶片具有集成的通过基板通孔（TSV）。 半导体晶片包括基板。 电介质层可以形成在衬底的第一侧上。 穿通基板通孔可以延伸通过介电层和基板。 贯通基板通孔可以包括导电材料和隔离层。 隔离层可以至少部分地围绕导电材料。 隔离层可以具有锥形部分。

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