公开(公告)号：US20150109870A1

公开(公告)日：2015-04-23

申请号：US14515949

申请日：2014-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C5/14 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: An arithmetic processing unit including an SRAM with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells. The memory cells include inverters in which capacitors for backing up data are provided. When data of all the memory cells in a region is not rewritten after data is returned from the capacitors to the inverters, data in the region is not transferred from the inverters to the capacitors and the inverters are turned off. When data of at least one of the memory cells in the region is rewritten, data in the region is transferred from the inverters to the capacitors and then power of the inverters are turned off. In this manner, backup is selectively performed to reduce power consumption. Other embodiments are described and claimed.

Abstract translation: 一种算术处理单元，包括具有低功耗的SRAM，并执行备份和恢复操作，而不会对电路造成负担。 一个实施例是包括多个存储单元的存储器件。 存储单元包括其中提供用于备份数据的电容器的反相器。 在数据从电容器返回到逆变器之后，当区域中的所有存储单元的数据不被重写时，该区域中的数据不会从反相器传送到电容器，并且反相器被关断。 当该区域中的至少一个存储单元的数据被重写时，该区域中的数据从反相器传送到电容器，然后逆变器的电源被关断。 以这种方式，选择性地执行备份以降低功耗。 描述和要求保护其他实施例。

公开(公告)号：US08994400B2

公开(公告)日：2015-03-31

申请号：US13872286

申请日：2013-04-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: G11C11/24 ,  H03K19/173 ,  G11C14/00 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12

CPC classification number: H03K3/037 ,  G11C11/24 ,  G11C14/0054 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/7869 ,  H03K19/173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Abstract translation: 为了提供使用非易失性锁存电路的新型非易失性锁存电路和半导体器件，非易失性锁存电路包括具有环形结构的锁存部分，其中第一元件的输出电连接到第二元件的输入端，输出端 的第二元件电连接到第一元件的输入端; 以及数据保持部，被配置为保持所述锁存部的数据。 在数据保持部分中，使用使用氧化物半导体作为形成沟道形成区域的半导体材料的晶体管作为开关元件。 此外，还包括与晶体管的源电极或漏电极电连接的电容器。

公开(公告)号：US20150069138A1

公开(公告)日：2015-03-12

申请号：US14541269

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H01L27/12 ,  H01L29/786 ,  G06K19/077 ,  H01L29/10

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

Abstract translation: 目的是实现具有无线通信功能的半导体器件的低功耗和长寿命。 可以通过使用氧化物半导体形成沟道形成区域的晶体管将用作电源和特定电路的电池彼此电连接的方式实现目的。 氧化物半导体的氢浓度低于或等于5×1019（原子/ cm3）。 因此，可以减小晶体管的漏电流。 结果，可以降低处于待机状态的半导体器件的功耗。 此外，半导体器件可以具有长的寿命。

公开(公告)号：US20150022251A1

公开(公告)日：2015-01-22

申请号：US14510310

申请日：2014-10-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/356 ,  H03K3/037

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Abstract translation: 为了提供使用非易失性锁存电路的新型非易失性锁存电路和半导体器件，非易失性锁存电路包括具有环形结构的锁存部分，其中第一元件的输出电连接到第二元件的输入端，输出端 的第二元件电连接到第一元件的输入端; 以及用于保持锁存部分的数据的数据保持部分。 在数据保持部分中，使用使用氧化物半导体作为形成沟道形成区域的半导体材料的晶体管作为开关元件。 此外，还包括与晶体管的源电极或漏电极电连接的反相器。 利用晶体管，保持在锁存部分中的数据可以写入逆变器的栅极电容器或单独提供的电容器。

公开(公告)号：US20140319518A1

公开(公告)日：2014-10-30

申请号：US14328818

申请日：2014-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

Abstract translation: 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

公开(公告)号：US08860485B2

公开(公告)日：2014-10-14

申请号：US13854176

申请日：2013-04-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/00 ,  H03K3/037 ,  H01L27/12 ,  H03K3/286 ,  G11C14/00 ,  G11C7/04 ,  H03K3/356 ,  H01L27/105 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  G11C16/04

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Abstract translation: 为了提供使用非易失性锁存电路的新型非易失性锁存电路和半导体器件，非易失性锁存电路包括具有环形结构的锁存部分，其中第一元件的输出电连接到第二元件的输入端，输出端 的第二元件电连接到第一元件的输入端; 以及用于保持锁存部分的数据的数据保持部分。 在数据保持部分中，使用使用氧化物半导体作为形成沟道形成区域的半导体材料的晶体管作为开关元件。 此外，还包括与晶体管的源电极或漏电极电连接的反相器。 利用晶体管，保持在锁存部分中的数据可以写入逆变器的栅极电容器或单独提供的电容器。

公开(公告)号：US08847326B2

公开(公告)日：2014-09-30

申请号：US13913591

申请日：2013-06-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

IPC: H01L27/088 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L27/088 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(∈ra/∈rb)

Abstract translation: 具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。 第一晶体管和第二晶体管被设置为至少部分地彼此重叠。 第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（∈ra/∈rb）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示第 绝缘层，∈ra表示栅极绝缘层的介电常数，∈rb表示绝缘层的介电常数。

公开(公告)号：US20140203859A1

公开(公告)日：2014-07-24

申请号：US14160774

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K5/04

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract translation: 提供能够调整时钟信号或高质量半导体器件的定时的半导体器件。 半导体器件包括第一晶体管和包括第二晶体管的电路。 第一晶体管的沟道形成在氧化物半导体层中。 第一信号被输入到第一晶体管的源极和漏极之一。 第一晶体管的源极和漏极中的另一个电连接到第二晶体管的栅极。 第一时钟信号被输入到电路。 电路输出第二个时钟信号。 第二时钟信号的定时与第一时钟信号的定时不同。

公开(公告)号：US20140138778A1

公开(公告)日：2014-05-22

申请号：US14162837

申请日：2014-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L27/105

CPC classification number: H01L27/1052 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

Abstract translation: 本发明的目的是提供具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保持存储的数据，并且对写入操作的数量没有限制。 该半导体器件包括：第一存储单元，包括第一晶体管和第二晶体管;第二存储单元，包括第三晶体管和第四晶体管;以及驱动电路。 第一晶体管和第二晶体管至少部分地彼此重叠。 第三晶体管和第四晶体管至少部分地彼此重叠。 第二存储单元设置在第一存储单元上。 第一晶体管包括第一半导体材料。 第二晶体管，第三晶体管和第四晶体管包括第二半导体材料。

公开(公告)号：US20140121787A1

公开(公告)日：2014-05-01

申请号：US14062249

申请日：2013-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC: G05B15/02

CPC classification number: H02M3/156 ,  G01R19/00 ,  G05B15/02 ,  G05B19/048 ,  G05B2219/24024 ,  G06F1/32 ,  G08B26/007 ,  G08B29/181 ,  H04L12/2825 ,  H04W4/043 ,  Y02B90/241 ,  Y02D70/00 ,  Y02D70/144 ,  Y04S20/242 ,  Y04S20/32 ,  Y04S20/36

Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.

Abstract translation: 提供一种能够集中控制电气设备和传感器设备的结构以及可以降低电气设备和传感器设备的功耗的结构。 中央控制系统至少包括中央控制装置，输出单元以及电气装置或传感器装置。 中央控制装置对从电气装置或传感器装置发送的信息进行运算处理，并且通过运算处理得到输出部输出信息。 除了电气装置或传感器装置之外，还可以知道电气装置或传感器装置的状态。 电气装置或传感器装置包括晶体管，其包括使用具有比单晶硅更宽的带隙的半导体的激活层。