公开(公告)号：US20230377954A1

公开(公告)日：2023-11-23

申请号：US18363865

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L23/5329 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

公开(公告)号：US20230369420A1

公开(公告)日：2023-11-16

申请号：US18357264

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H10B51/00

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.

公开(公告)号：US20230329000A1

公开(公告)日：2023-10-12

申请号：US18335167

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/78687 ,  H01L29/7869 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78648 ,  H01L29/66765 ,  H01L29/78693 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US20230299003A1

公开(公告)日：2023-09-21

申请号：US18321077

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L23/5329 ,  H01L21/76837 ,  H01L21/02282 ,  H01L21/02216 ,  H01L21/02203 ,  H01L21/02126 ,  H01L21/7682 ,  H01L23/53295 ,  H01L29/0649 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/585 ,  H01L23/3178 ,  H01L29/0642 ,  H01L23/3185 ,  H01L2221/1047

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

公开(公告)号：US20230247841A1

公开(公告)日：2023-08-03

申请号：US17591174

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1159 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/42324

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

公开(公告)号：US11653501B2

公开(公告)日：2023-05-16

申请号：US17352339

申请日：2021-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/78 ,  H01L23/528 ,  H01L27/1159 ,  H01L27/11553 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11597 ,  H01L23/5283 ,  H01L27/1159 ,  H01L27/11553 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78391

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

公开(公告)号：US20230074585A1

公开(公告)日：2023-03-09

申请号：US17987066

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US11532552B2

公开(公告)日：2022-12-20

申请号：US17120601

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsu Wu ,  Hai-Ching Chen ,  Jung-Hsun Tsai ,  Shau-Lin Shue ,  Tien-I Bao

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

公开(公告)号：US20220293512A1

公开(公告)日：2022-09-15

申请号：US17829590

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/538

Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

公开(公告)号：US20220293462A1

公开(公告)日：2022-09-15

申请号：US17829611

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.