公开(公告)号：US10411021B2

公开(公告)日：2019-09-10

申请号：US15897424

申请日：2018-02-15

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L29/423 ,  H01L27/06 ,  H01L29/78

摘要： A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

公开(公告)号：US10381451B2

公开(公告)日：2019-08-13

申请号：US15788353

申请日：2017-10-19

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/49 ,  H01L29/786

摘要： A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.

公开(公告)号：US10186601B2

公开(公告)日：2019-01-22

申请号：US15342217

申请日：2016-11-03

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L29/786

摘要： A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.

公开(公告)号：US10002934B2

公开(公告)日：2018-06-19

申请号：US14602729

申请日：2015-01-22

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L27/02

CPC分类号： H01L29/42392 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/16 ,  H01L29/7827

摘要： A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

公开(公告)号：US09905755B2

公开(公告)日：2018-02-27

申请号：US15489237

申请日：2017-04-17

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L27/01 ,  H01L31/113 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L45/00 ,  H01L27/108 ,  H01L29/66 ,  G11C13/00 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L45/04 ,  G11C13/0002 ,  H01L27/0886 ,  H01L27/10879 ,  H01L27/2454 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A semiconductor device includes first pillar-shaped silicon layers, a first gate insulating film formed around the first pillar-shaped silicon layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped silicon layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped silicon layers, diffusion layers formed in lower portions of the first pillar-shaped silicon layers, and variable-resistance memory elements formed on the second contacts.

公开(公告)号：US09865535B2

公开(公告)日：2018-01-09

申请号：US15346176

申请日：2016-11-08

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Nozomu Harada

IPC分类号： H01L29/66 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786 ,  H01L27/11 ,  H01L23/532

CPC分类号： H01L23/5228 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78642

摘要： A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer formed on the interconnection layer, a semiconductor-metal compound layer formed so as to cover the entire upper surface of the interconnection layer except for a bottom portion of the first pillar-shaped semiconductor layer, a first gate insulating film surrounding the first pillar-shaped semiconductor layer, a first gate electrode surrounding the first gate insulating film, and a first gate line connected to the first gate electrode.

公开(公告)号：US09825221B2

公开(公告)日：2017-11-21

申请号：US15019553

申请日：2016-02-09

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L31/119 ,  H01L29/06 ,  H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

摘要： A memory device includes a reset gate whose resistance changes. The memory device also includes a pillar-shaped phase-change layer, a reset gate insulating film surrounding the pillar-shaped phase-change layer, and the reset gate surrounding the reset gate insulating film. The pillar-shaped phase-change layer and the reset gate are electrically insulated from each other by the reset gate insulating film.

公开(公告)号：US09812547B2

公开(公告)日：2017-11-07

申请号：US15467627

申请日：2017-03-23

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/00 ,  H01L29/49 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/417 ,  H01L27/088

CPC分类号： H01L29/4966 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L29/0676 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.

公开(公告)号：US09768267B2

公开(公告)日：2017-09-19

申请号：US14755317

申请日：2015-06-30

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42356 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/3213 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

摘要： An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion of the fin-shaped layer, forming a second insulating film, a polysilicon gate electrode covering the second insulating film, and a polysilicon gate line, forming a diffusion layer in an upper portion of the fin-shaped layer and a lower portion of the pillar-shaped layer, forming a metal-semiconductor compound in an upper portion of the diffusion layer in the fin-shaped layer, depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and gate line, depositing a first metal, forming a metal gate electrode and a metal gate line, and forming a third metal sidewall on an upper side wall of the pillar-shaped layer. The third metal sidewall is connected to an upper surface of the pillar-shaped layer.

公开(公告)号：US09666712B2

公开(公告)日：2017-05-30

申请号：US15230664

申请日：2016-08-08

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L21/308 ,  H01L29/40 ,  H01L29/417 ,  H01L23/528 ,  H01L29/10

CPC分类号： H01L29/7827 ,  H01L21/3083 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.