公开(公告)号：US20240126017A1

公开(公告)日：2024-04-18

申请号：US18046840

申请日：2022-10-14

Applicant: ProMOS Technologies Inc.

Inventor： Ping Ming Liu ,  Hsiao Che Wu

IPC: G02B6/30

CPC classification number: G02B6/305

Abstract: A photonic integrated circuit structure includes a substrate, a waveguide structure and a spot size converter. The waveguide structure is disposed over a surface of the substrate and has a receiving end. The spot size converter includes a concave mirror and a curved mirror. The concave mirror and the curved mirror are opposite to each other and have a common focus. The concave mirror is arranged to reflect a parallel beam from a transmitting end such that a first reflected beam is able to converge at the common focus, and the curved mirror is arranged to reflect the first reflected beam such that a second reflected beam is directed parallel to the receiving end of the waveguide structure.

公开(公告)号：US07897431B2

公开(公告)日：2011-03-01

申请号：US12348403

申请日：2009-01-05

Applicant: Min-Liang Chen ,  Hai-Jun Zhao

Inventor： Min-Liang Chen ,  Hai-Jun Zhao

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48

CPC classification number: H01L21/8221 ,  H01L23/481 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/81894 ,  H01L2224/83856 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer.

Abstract translation: 堆叠晶片的方法包括：提供包括第一金属连接层的第一晶片; 在所述第一金属连接层上形成第一钝化层; 在所述第一钝化层中形成第一接合焊盘以形成第一接合焊盘层; 提供包括第二金属连接层的第二晶片; 在所述第二金属连接层上形成第二钝化层; 在所述第二钝化层中形成第二接合焊盘以形成第二接合焊盘层; 在所述第一接合垫层上形成第一导电粘合剂层中的至少一个，并且在所述第二接合焊盘层上方形成第二导电粘合剂层; 以及通过所述第一导电粘合剂层和所述第二导电粘合剂层中的至少一个将所述第二接合焊盘层的各个表面与所述第一接合焊盘层接合来将所述第二晶片堆叠在所述第一晶片上。

公开(公告)号：US07872307B2

公开(公告)日：2011-01-18

申请号：US12115552

申请日：2008-05-06

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.

Abstract translation: 提供功率金属氧化物半导体场效应晶体管（MOSFET）阵列结构。 功率MOSFET阵列设置在栅极焊盘下方，栅极焊盘下方的空间可以很好地用于增加器件集成度。 当通过使用电路连接区域将阵列和设置在源极焊盘下面的常规功率MOSFET阵列连接到阵列对时，可以共享相同的栅极焊盘和源极焊盘，从而达到增加器件集成度的目的。

公开(公告)号：US20100163828A1

公开(公告)日：2010-07-01

申请号：US12464014

申请日：2009-05-11

Applicant: Li-Shu Tu

Inventor： Li-Shu Tu

IPC: H01L45/00 ,  H01L21/20

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer.

Abstract translation: 提供了一种相变存储器件，包括其上设置有第一导电半导体层的半导体衬底，其中第一导电半导体层具有第一导电类型。 第一电介质层设置在半导体衬底之上。 具有与第一导电类型相反的第二导电类型的第二导电半导体层设置在第一电介质层中。 加热电极设置在第一电介质层中并形成在第二导电半导体层上，其中加热电极具有锥形横截面并且包括金属硅化物。 第二介电层设置在第一介电层上。 相变材料层设置在第二电介质层中。 电极设置在第二电介质层上，覆盖相变材料层。

公开(公告)号：US07732801B2

公开(公告)日：2010-06-08

申请号：US11797730

申请日：2007-05-07

Applicant: Wei-Su Chen

Inventor： Wei-Su Chen

IPC: H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/148 ,  H01L45/1691

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on the first phase change memory structure and electrically connected to the first phase change memory structure, wherein the first or second phase change memory structure includes a cup-shaped heating electrode. A first insulating layer covers a portion of the cup-shaped heating electrode along a first direction. A first electrode structure covers a portion of the first insulating layer and the cup-shaped heating electrode along a second direction. The first electrode structure includes a pair of phase change material sidewalls on a pair of sidewalls of the first electrode structure and covering a portion of the cup-shaped heating electrode.

Abstract translation: 提供了相变存储器件。 相变存储器件包括其上形成有第一电极层的衬底。 第一相变存储器结构在第一电极层上并且电连接到第一电极层。 第二相变存储器结构位于第一相变存储器结构上并电连接到第一相变存储器结构，其中第一或第二相变存储器结构包括杯形加热电极。 第一绝缘层沿着第一方向覆盖杯形加热电极的一部分。 第一电极结构沿第二方向覆盖第一绝缘层和杯形加热电极的一部分。 第一电极结构包括在第一电极结构的一对侧壁上的一对相变材料侧壁，并且覆盖杯形加热电极的一部分。

公开(公告)号：US07679163B2

公开(公告)日：2010-03-16

申请号：US11748440

申请日：2007-05-14

Applicant: Frederick T Chen ,  Ming-Jinn Tsai

Inventor： Frederick T Chen ,  Ming-Jinn Tsai

IPC: H01L29/04 ,  H01L29/00

CPC classification number: H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract translation: 公开了一种用于减少热损失的相变存储元件。 相变存储元件包括复合层，其中复合层包括电介质材料和低热导率材料。 在复合层内形成通孔。 相变材料占据通孔的至少一部分。 复合层包括交替的层或介电材料和低热导率材料的混合物。

公开(公告)号：US20100062593A1

公开(公告)日：2010-03-11

申请号：US12207740

申请日：2008-09-10

Applicant: CHUNG WE PAN ,  MING YU HO ,  CHIH PING CHUNG

Inventor： CHUNG WE PAN ,  MING YU HO ,  CHIH PING CHUNG

IPC: H01L21/28

CPC classification number: H01L29/7923 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression.

Abstract translation: 一种制备多电平闪速存储器件的方法包括在半导体衬底上形成包含电荷俘获层的电介质叠层，形成在电荷俘获层上具有凹陷的绝缘结构，去除一部分电荷俘获层 从凹陷处使得电荷捕获层被分段以形成多个存储节点，形成隔离存储节点的栅氧化层，并形成包括填充凹陷的多晶硅层的镶嵌栅极。

公开(公告)号：US20100013004A1

公开(公告)日：2010-01-21

申请号：US12174110

申请日：2008-07-16

Applicant: HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

Inventor： HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

IPC: H01L29/78

CPC classification number: H01L29/7834 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract translation: 凹陷沟道晶体管包括具有沟槽隔离结构的半导体衬底，在半导体衬底中具有下部块的栅极结构和位于半导体衬底上的上部块，位于上部块的两侧和下部块上方的两个掺杂区域 以及位于上块的侧壁处并且具有夹在上块和掺杂区之间的底端的绝缘垫片。 特别地，两个掺杂区域分别用作源极和漏极区，并且栅极结构的下部块用作凹陷沟道晶体管的凹入栅极。

公开(公告)号：US07635626B2

公开(公告)日：2009-12-22

申请号：US11767222

申请日：2007-06-22

Applicant: Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

Inventor： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

IPC: H01L21/8242

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76855 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Abstract translation: 制造DRAM的方法包括首先提供衬底。 然后在衬底上形成许多晶体管。 接下来，在晶体管之间形成第一和第二LPC。 然后在衬底上形成第一电介质层，并且在第一电介质层中形成暴露第一LPC的第一开口。 此后，在第一电介质层上形成阻挡层。 之后，在第一开口中形成BLC，在第一介电层上形成BL。 然后在BL的侧壁上形成衬垫层。 接下来，在基板上形成具有与衬垫层的干蚀刻速率基本相等且具有大于衬层的湿刻蚀速率的干蚀刻速率的第二介质层。 最后，在第一和第二电介质层中形成SNC。

公开(公告)号：US07622352B2

公开(公告)日：2009-11-24

申请号：US11440075

申请日：2006-05-25

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1037 ,  H01L21/28114 ,  H01L21/28141 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/66659

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract translation: 多级栅极结构包括具有多级结构的半导体衬底，位于多级结构上的栅极氧化物层和位于栅极氧化物层上的导电层。 优选地，栅极氧化物层在多步骤结构的每个台阶表面上具有不同的厚度。 此外，多步栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域。 多级栅极结构的沟道长度是多级栅极结构的横向宽度和垂直深度的总和，其显着增加，从而可以有效地解决源自短沟道效应的问题。 此外，通过注入具有不同剂量和掺杂剂的工艺来制备多步结构下的多个掺杂区域，其可以控制栅极氧化物层的厚度和多步栅极结构的阈值电压。