公开(公告)号：US20180166128A1

公开(公告)日：2018-06-14

申请号：US15375987

申请日：2016-12-12

申请人： STMicroelectronics International N.V.

发明人： Harsh Rawat ,  Abhishek Pathak

IPC分类号： G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC分类号： G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

摘要： A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US09996104B2

公开(公告)日：2018-06-12

申请号：US15475298

申请日：2017-03-31

申请人： Huawei Technologies Co., Ltd.

发明人： Tao Huang

IPC分类号： G06F15/78 ,  G06F1/08

CPC分类号： G06F1/08 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/78 ,  G06F15/781

摘要： A frequency adjustment method, a System-On-a-Chip, and a terminal are provided. In the embodiments of this application, when an access bandwidth requirement on a DDR memory changes, a first frequency adjustment request for a DDR interface is generated using a CPU, and a working frequency of the DDR interface is adjusted. Because during adjustment of the working frequency of the DDR interface, the working frequency of the DDR interface is gradually adjusted according to a predetermined adjustment amount by which a frequency adjustment coefficient of a spread spectrum clocking generator is adjusted each time and a predetermined interval between two adjacent adjustments, it is ensured that a DLL in the DDR interface and a phase-locked loop in the spread spectrum clocking generator are in locking-in states, so that the DDR memory can still be accessed during frequency adjustment of the DDR interface and system performance is ensured.

公开(公告)号：US09990984B1

公开(公告)日：2018-06-05

申请号：US15370892

申请日：2016-12-06

申请人： QUALCOMM Incorporated

发明人： Dorav Kumar ,  Venkat Narayanan ,  Bilal Zafar ,  Seid Hadi Rasouli ,  Venugopal Boynapalli

IPC分类号： G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC分类号： G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

摘要： The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

公开(公告)号：US09977607B2

公开(公告)日：2018-05-22

申请号：US15671971

申请日：2017-08-08

申请人： Mag Instrument, Inc.

发明人： Stacey West

IPC分类号： H05B37/00 ,  G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC分类号： G06F3/0611 ,  F21L4/00 ,  F21V23/0428 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  H05B33/0845 ,  H05B33/0854 ,  H05B37/0209 ,  Y02B20/40 ,  Y02D10/14 ,  Y02D10/151

摘要： A portable lighting device that provides different user interfaces that may be selected by the user. Each user interface may provide one or more operational modes, such as on mode, power save mode, strobe mode or momentary mode. After a user interface is selected, the user may select on of the operational modes. The portable lighting device may be a flashlight.

公开(公告)号：US09959185B2

公开(公告)日：2018-05-01

申请号：US15140492

申请日：2016-04-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hsin-Wen Chen

IPC分类号： G06F11/00 ,  G06F11/27 ,  G06F13/16 ,  G06F11/22

CPC分类号： G06F11/27 ,  G06F11/2289 ,  G06F13/1689

摘要： A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.

公开(公告)号：US20180095916A1

公开(公告)日：2018-04-05

申请号：US15702987

申请日：2017-09-13

申请人： Rambus Inc.

发明人： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC分类号： G06F13/364 ,  G06F13/42 ,  G06F1/10 ,  G06F3/06 ,  G06F12/02 ,  G11C7/10

CPC分类号： G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

公开(公告)号：US20180095910A1

公开(公告)日：2018-04-05

申请号：US15283396

申请日：2016-10-01

申请人： Intel Corporation

发明人： Stanley Steve KULICK ,  Bezan KAPADIA ,  James SHEHADI ,  Amir Ali RADJAI

IPC分类号： G06F13/16 ,  G06F13/40

CPC分类号： G06F13/1689 ,  G06F13/1673 ,  G06F13/4068

摘要： A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.

公开(公告)号：US20180082725A1

公开(公告)日：2018-03-22

申请号：US15665312

申请日：2017-07-31

申请人： Rambus Inc.

发明人： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC分类号： G11C7/22 ,  G06F13/16 ,  G11C7/02

CPC分类号： G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

摘要： A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US20180077087A1

公开(公告)日：2018-03-15

申请号：US15817180

申请日：2017-11-18

申请人： Fortinet, Inc.

发明人： Xu Zhou ,  David Chen ,  Lin Huang ,  Guansong Zhang

IPC分类号： H04L12/935 ,  H04L29/06 ,  H04L12/863 ,  G06F13/16

CPC分类号： H04L49/3045 ,  G06F12/1081 ,  G06F13/1689 ,  G06F2212/657 ,  H04L47/62 ,  H04L47/621 ,  H04L69/166

摘要： Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, presence of outbound payload data, distributed across a first and second payload buffer, within a user memory space of a network device that has been generated by a user process is determined by a bus/memory interface or a network interface unit. The payload data is fetched by performing direct virtual memory addressing of the user memory space including mapping virtual addresses of the payload buffers to corresponding physical addresses, including: (i) when the payload buffers are noncontiguous, then retrieving the outbound payload data with reference to multiple buffer descriptors having starting virtual addresses of the payload buffers and (ii) when they are contiguous, then retrieving the outbound payload data with reference to a single buffer descriptor. The outbound payload data is then segmented across one or more TCP packets.

公开(公告)号：US09916098B2

公开(公告)日：2018-03-13

申请号：US15114098

申请日：2014-01-31

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Raphael Gay ,  Siamak Tavallaei

IPC分类号： G06F12/08 ,  G06F3/06 ,  G06F13/16 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0638 ,  G06F12/0802 ,  G06F13/1689 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/60

摘要： Example implementations relate to using an alternative memory (AltMem) to reduce read latency of a memory module having a dynamic random-access memory (DRAM). In example implementations, write data may be written to the DRAM and to the AltMem. A read command may be issued to the AltMem if a DRAM read latency time for executing the read command is greater than an AltMem read latency time for executing the read command. Data read from the AltMem in response to the read command may be received.