公开(公告)号：US06975012B2

公开(公告)日：2005-12-13

申请号：US10697129

申请日：2003-10-29

申请人： Miki Moriyama ,  Masaki Murakami ,  Atsushi Kyan ,  Ryoichi Ohno

发明人： Miki Moriyama ,  Masaki Murakami ,  Atsushi Kyan ,  Ryoichi Ohno

IPC分类号： G01T1/24 ,  H01L27/14 ,  H01L31/0224 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/09 ,  H01L31/108 ,  H01L31/118 ,  H01L31/07 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L31/022408 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/118

摘要： Disclosed is a semiconductor radiation detector element of Schottky barrier type, comprising: a compound semiconductor crystal including cadmium and tellurium as main components; and voltage application means for applying voltage to the compound semiconductor crystal. According to the present invention, said voltage application means includes a compound of indium, cadmium and tellurium: InxCdyTez formed on one surface of the compound semiconductor crystal. Preferably, the rate “z” of occupation of tellurium in the compound InxCdyTez is in the range of not less than 42.9%, but not greater than 50% by ratio of number of atoms. Furthermore, preferably, the rate “y” of occupation of cadmium in the compound InxCdyTez is in the range of not less than 0%, but not greater than 10% by ratio of number of atoms.

摘要翻译： 公开了一种肖特基势垒型半导体辐射检测元件，其特征在于，包括：以镉和碲为主要成分的化合物半导体晶体; 以及用于向化合物半导体晶体施加电压的电压施加装置。 根据本发明，所述电压施加装置包括铟，镉和碲的化合物：在一个上形成的一个或多个Cd 化合物半导体晶体的表面。 优选地，化合物中的碲的占据率“z”在不小于42.9的范围内 ％，但不大于50％的原子数比。 此外，优选地，化合物中的Cd的占据的比率“y”在不小于 超过原子数的0％，但不大于10％。

公开(公告)号：US20050218399A1

公开(公告)日：2005-10-06

申请号：US10515763

申请日：2003-05-27

申请人： Petrus Magnee ,  Johannes Josephus Donkers

发明人： Petrus Magnee ,  Johannes Josephus Donkers

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L29/06 ,  H01L21/8222 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L31/11 ,  H01L31/117

CPC分类号： H01L29/66242

摘要： The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), etching a transistor area opening (12, 44) through the conductive layer (14, 42), depositing a SiGe base layer (24, 46) on the inner wall of the transistor area opening (22, 44) and forming an insulator (32, 52) on an upper surface so as to fill the transistor area opening wherein prior to the filling step, a nitride layer (30, 50) is formed as an inner layer of the transistor area opening (22, 44).

摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件包括非选择性生长的SiGe（C）异质结双极晶体管，包括以下步骤：在衬底上形成绝缘层（12,40），并提供包括导电层 （14,42），通过所述导电层（14,42）蚀刻晶体管区域开口（12,44），在所述绝缘层（12,40）的内壁上沉积SiGe基底层（24,46） 所述晶体管区域开口（22,44）并且在上表面上形成绝缘体（32,52）以便填充晶体管区域开口，其中在填充步骤之前，将氮化物层（30,50）形成为内部 晶体管区域开口（22,44）的层。

公开(公告)号：US06917096B2

公开(公告)日：2005-07-12

申请号：US10611157

申请日：2003-07-02

申请人： Naoharu Sugiyama ,  Atsushi Kurobe ,  Tsutomu Tezuka ,  Tomohisa Mizuno ,  Shinichi Takagi

发明人： Naoharu Sugiyama ,  Atsushi Kurobe ,  Tsutomu Tezuka ,  Tomohisa Mizuno ,  Shinichi Takagi

IPC分类号： H01L21/205 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/84 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L31/117

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/28255 ,  H01L21/31675 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/78687 ,  Y10S438/938

摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

摘要翻译： 半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层 形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道， 以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

公开(公告)号：US06900521B2

公开(公告)日：2005-05-31

申请号：US10164611

申请日：2002-06-10

申请人： Leonard Forbes ,  Kie Y. Ahn

发明人： Leonard Forbes ,  Kie Y. Ahn

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/76 ,  H01L31/117

CPC分类号： H01L27/092 ,  H01L21/823885 ,  H01L27/11807 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827

摘要： Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

摘要翻译： 公开了包括具有超薄垂直NMOS晶体管的CMOS门阵列的非常快速的集成OPL电路，例如伪NMOS OPL和动态OPL。 CMOS栅极阵列的超薄垂直NMOS晶体管由具有梯度锗含量和应变硅通道的松弛硅锗（SiGe）体区形成。

公开(公告)号：US20050106801A1

公开(公告)日：2005-05-19

申请号：US11001334

申请日：2004-12-02

申请人： Satoshi Matsuda ,  Kazuya Ohuchi

发明人： Satoshi Matsuda ,  Kazuya Ohuchi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861 ,  H01L31/0392 ,  H01L31/113 ,  H01L31/117 ,  H01L31/119

CPC分类号： H01L29/861 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L29/16 ,  H01L29/665

摘要： A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a silicide film which extends from the N type diffusion layer over to the boundary region and the P-type diffusion layer. A boundary region between the P-type and N-type diffusion layers is formed in the selected portion.

摘要翻译： 制造半导体器件的方法包括将锗离子注入到至少含有硅的半导体区域的选定部分中，在半导体区域中形成P型和N型扩散层，并形成从N型 扩散层到边界区域和P型扩散层。 在所选择的部分中形成P型和N型扩散层之间的边界区域。

公开(公告)号：US6043549A

公开(公告)日：2000-03-28

申请号：US45551

申请日：1998-03-20

申请人： Augusto L. Gutierrez-Aitken

发明人： Augusto L. Gutierrez-Aitken

IPC分类号： H01L31/0232 ,  H01L31/0352 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L31/0232 ,  H01L31/0352

摘要： A photodetector having improved responsivity includes first, second and third contact layers and first and second absorption layers. The first and second absorption layers are disposed on opposite sides of the first contact layer. The second contact layer is disposed on the first absorption layer and the third contact layer is disposed on the second absorption layer. The first contact layer has a first polarity. The second and third contact layers have a second polarity which is opposite the first polarity. Preferably, the first and second absorption layers are each made of a material having approximately equivalent electrical characteristics and the second and third contact layers are interconnected. Alternatively, one absorption layer is responsive to a first wavelength and another absorption layer is responsive to a second wavelength.

摘要翻译： 具有改进的响应度的光电检测器包括第一，第二和第三接触层以及第一和第二吸收层。 第一和第二吸收层设置在第一接触层的相对侧上。 第二接触层设置在第一吸收层上，第三接触层设置在第二吸收层上。 第一接触层具有第一极性。 第二和第三接触层具有与第一极性相反的第二极性。 优选地，第一和第二吸收层各自由具有近似等效电特性的材料制成，并且第二和第三接触层互连。 或者，一个吸收层响应于第一波长，另一个吸收层响应于第二波长。

公开(公告)号：US5844292A

公开(公告)日：1998-12-01

申请号：US679467

申请日：1996-07-15

申请人： Pochet Thierry

发明人： Pochet Thierry

IPC分类号： H01L27/146 ,  H01L31/10 ,  H01L31/105 ,  H04N5/335 ,  H01L31/075 ,  H01L31/117

CPC分类号： H01L27/1465 ,  H01L31/1055

摘要： A photosensitive device, e.g. for use as an optical sensor for a video camera, is designed to capture light and to deliver an electrical signal representative of the captured light, and presenting a resistance to hard electromagnetic radiation. The device includes a photosensitive element in hydrogenated amorphous silicon and a collector for the electrical charges induced by the photoelectric effect in the photosensitive element capturing the light and for delivering an electrical signal resulting therefrom. The device is electrically connected to an electronic processor for processing the electrical signal.

摘要翻译： 感光装置，例如 用作摄像机的光学传感器，被设计为捕获光并传送代表所捕获的光的电信号，并呈现出对硬电磁辐射的抵抗力。 该装置包括氢化非晶硅中的光敏元件和用于由感光元件中的光电效应引起的电荷的收集器，该光电效应捕获光并输送由此产生的电信号。 该装置电连接到用于处理电信号的电子处理器。

公开(公告)号：US5818096A

公开(公告)日：1998-10-06

申请号：US832297

申请日：1997-04-03

申请人： Tadao Ishibashi ,  Tomofumi Furuta ,  Naofumi Shimizu ,  Koichi Nagata ,  Yutaka Matsuoka ,  Masaaki Tomizawa

发明人： Tadao Ishibashi ,  Tomofumi Furuta ,  Naofumi Shimizu ,  Koichi Nagata ,  Yutaka Matsuoka ,  Masaaki Tomizawa

IPC分类号： H01L31/105 ,  H01L31/075 ,  H01L31/107 ,  H01L31/117

CPC分类号： H01L31/105

摘要： A pin photodiode having a structure capable improving the frequency response and the saturation output while maintaining the effective internal quantum efficiency and CR time constant. A pin photodiode is formed by: a first semiconductor layer in a first conduction type; a second semiconductor layer in a second conduction type; a third semiconductor layer sandwiched between the first and second semiconductor layers, having a doping concentration lower than those of the first and second semiconductor layers; a fourth semiconductor layer in the first conduction type, provided at one side of the first semiconductor layer opposite to a side at which the third semiconductor layer is provided; and a cathode electrode and an anode electrode connected directly or indirectly to the second semiconductor layer and the fourth semiconductor layer, respectively. The first semiconductor layer has a bandgap energy by which a charge neutrality condition is maintained in at least a part of the first semiconductor layer and the first semiconductor layer is made to function as a light absorption layer, while the second and third semiconductor layers have bandgap energies by which the second and third semiconductor layers are made not to function as a light absorption layer, and the fourth semiconductor layer has a bandgap energy greater than that of the first semiconductor layer.

摘要翻译： 具有能够在保持有效内部量子效率和CR时间常数的同时提高频率响应和饱和输出的结构的引脚光电二极管。 pin光电二极管是通过以下方式形成的：第一导电类型的第一半导体层; 第二导电类型的第二半导体层; 夹在第一和第二半导体层之间的第三半导体层，其掺杂浓度低于第一和第二半导体层的掺杂浓度; 第一导电型的第四半导体层，设置在与设置有第三半导体层的一侧相反的第一半导体层的一侧; 以及分别直接或间接地连接到第二半导体层和第四半导体层的阴极电极和阳极电极。 第一半导体层具有带隙能量，在第一半导体层的至少一部分中保持电荷中性条件，并且使第一半导体层起光吸收层的作用，而第二和第三半导体层具有带隙 使得第二和第三半导体层不能用作光吸收层的能量，并且第四半导体层的带隙能量大于第一半导体层的能隙。

公开(公告)号：US5744850A

公开(公告)日：1998-04-28

申请号：US733967

申请日：1996-10-18

申请人： Keiji Sato ,  Yutaka Saitoh ,  Tadao Akamine

发明人： Keiji Sato ,  Yutaka Saitoh ,  Tadao Akamine

IPC分类号： H01L31/10 ,  H01L27/144 ,  H01L31/107 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L27/1443 ,  H01L31/107

摘要： A novel photoelectric conversion semiconductor device having an amplifying function which can be readily fabricated is provided. An N.sup.+ -type impurity domain whose impurity concentration is higher than that of an N.sup.- -type semiconductor substrate is formed on one surface thereof and a P.sup.+ -type impurity domain is formed on the opposite surface. An SiO.sub.2 film, an Si.sub.3 N.sub.4 film and an SiO.sub.2 film are formed extending to the domain of the N.sup.- -type semiconductor substrate, exceeding the N.sup.+ -type impurity domain. An anode electrode is formed on the N.sup.+ -type impurity domain and a cathode electrode is formed on the P.sup.+ -type impurity domain. A polysilicon gate electrode is formed on the SiO.sub.2 film, i.e. the top layer, and an Al gate electrode is formed thereon. A reverse voltage is applied between the anode electrode and the cathode electrode and a predetermined voltage is applied between the anode electrode and the Al gate electrode.

摘要翻译： 提供了具有可容易地制造的放大功能的新颖的光电转换半导体器件。 在其一个表面上形成杂质浓度高于N型半导体衬底的杂质浓度的N +型杂质区域，在相对的表面上形成P +型杂质区域。 形成了延伸到N型半导体衬底的超过N +型杂质域的SiO 2膜，Si 3 N 4膜和SiO 2膜。 在N +型杂质区域上形成阳极电极，在P +型杂质区域上形成阴极电极。 在SiO 2膜即顶层上形成多晶硅栅电极，在其上形成Al栅电极。 在阳极电极和阴极电极之间施加反向电压，并且在阳极电极和Al栅电极之间施加预定电压。

公开(公告)号：US5670798A

公开(公告)日：1997-09-23

申请号：US412971

申请日：1995-03-29

申请人： Jan Frederick Schetzina

发明人： Jan Frederick Schetzina

IPC分类号： H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L33/00 ,  H01L33/32 ,  H01L33/40 ,  H01S5/183 ,  H01S5/323 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L33/40 ,  H01L29/205 ,  H01L29/267 ,  H01L33/007 ,  H01L33/32 ,  H01L29/2003 ,  H01S5/183 ,  H01S5/32341

摘要： An integrated heterostructure of Group III-V nitride compound semiconductors is formed on a multicomponent platform which includes a substrate of monocrystalline silicon carbide and a non-nitride buffer layer of monocrystalline zinc oxide. The zinc oxide may be formed by molecular beam epitaxy (MBE) using an MBE effusion cell containing zinc, and a source of atomic oxygen, such as an MBE-compatible oxygen plasma source which converts molecular oxygen into atomic oxygen. An ohmic contact for a semiconductor device formed of Group III-V nitride compound semiconductor materials including a layer of aluminum nitride or aluminum gallium nitride, includes a continuously graded layer of aluminum gallium nitride and a layer of gallium nitride or an alloy thereof on the continuously graded layer. The continuously graded layer eliminates conduction or valence band offsets. A multiple quantum well may also be used instead of the continuously graded layer where the thickness of the layers of gallium nitride increase across the multiple quantum well. The ohmic contacts may be used for Group III-V nitride laser diodes, light emitting diodes, electron emitters, bipolar transistors and field effect transistors.

摘要翻译： 在包括单晶碳化硅的衬底和单晶氧化锌的非氮化物缓冲层的多组件平台上形成III-V族氮化物化合物半导体的集成异质结构。 氧化锌可以通过分子束外延（MBE）使用含有锌的MBE渗出电池和原子氧源（例如将分子氧转化为原子氧）的MBE兼容的氧等离子体源形成。 由包含氮化铝或氮化镓的层的III-V族氮化物化合物半导体材料形成的半导体器件的欧姆接触包括连续梯度的氮化镓铝层和氮化镓层或其合金层 分级层。 连续梯度层消除传导或价带偏移。 也可以使用多量子阱代替连续梯度层，其中氮化镓层的厚度跨多个量子阱增加。 欧姆接触可用于III-V族氮化物激光二极管，发光二极管，电子发射器，双极晶体管和场效应晶体管。