公开(公告)号：US11769718B2

公开(公告)日：2023-09-26

申请号：US17815421

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  G01R1/04 ,  H01L21/48 ,  H01L21/683 ,  H01L23/32 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/46 ,  H05K7/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  G01R1/0433 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H05K1/141 ,  H05K3/4682 ,  H05K7/1053 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4694

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

公开(公告)号：US20230268317A1

公开(公告)日：2023-08-24

申请号：US18308900

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/467 ,  H01L23/473 ,  H01L23/367 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L25/50 ,  H01L23/467 ,  H01L23/473 ,  H01L23/367 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/481 ,  H01L2224/02311 ,  H01L24/26

Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

公开(公告)号：US11715755B2

公开(公告)日：2023-08-01

申请号：US16901912

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01G4/30

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US11670617B2

公开(公告)日：2023-06-06

申请号：US16939879

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/467 ,  H01L23/473 ,  H01L23/367 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/50 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/26 ,  H01L24/83 ,  H01L2224/02311 ,  H01L2224/18 ,  H01L2224/83895

Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

公开(公告)号：US11664349B2

公开(公告)日：2023-05-30

申请号：US17099395

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/80 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L21/568 ,  H01L22/32 ,  H01L23/3135 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/09517 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/821 ,  H01L2224/82031 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2224/821 ,  H05K3/467 ,  H01L2224/9222 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/80896 ,  H01L2924/00012

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

公开(公告)号：US11600551B2

公开(公告)日：2023-03-07

申请号：US16921561

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

公开(公告)号：US20220395953A1

公开(公告)日：2022-12-15

申请号：US17455116

申请日：2021-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Chang ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Ting-Chu Ko

IPC: B24B7/22 ,  B24B37/04 ,  B24B37/08 ,  B24B49/12

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

公开(公告)号：US20220384314A1

公开(公告)日：2022-12-01

申请号：US17883999

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US11495559B2

公开(公告)日：2022-11-08

申请号：US16859914

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.

公开(公告)号：US20220336356A1

公开(公告)日：2022-10-20

申请号：US17854683

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.