公开(公告)号：US20090140404A1

公开(公告)日：2009-06-04

申请号：US12038501

申请日：2008-02-27

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/10

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract translation: 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

公开(公告)号：US07521798B2

公开(公告)日：2009-04-21

申请号：US11943277

申请日：2007-11-20

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07488680B2

公开(公告)日：2009-02-10

申请号：US11214602

申请日：2005-08-30

Applicant: Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/4763

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

Abstract translation: 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US20090032920A1

公开(公告)日：2009-02-05

申请号：US12167745

申请日：2008-07-03

Applicant: Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

Inventor： Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract translation: 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US20080179755A1

公开(公告)日：2008-07-31

申请号：US11669924

申请日：2007-01-31

Applicant: Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

Abstract translation: 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US20080142958A1

公开(公告)日：2008-06-19

申请号：US12026776

申请日：2008-02-06

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornella K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornella K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/02

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

公开(公告)号：US07361581B2

公开(公告)日：2008-04-22

申请号：US10904677

申请日：2004-11-23

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/44

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

Abstract translation: 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US06963132B2

公开(公告)日：2005-11-08

申请号：US10447876

申请日：2003-05-29

Applicant: Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

Inventor： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

IPC: H01L21/68 ,  H01L23/34

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L2221/68363 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075

Abstract: The present invention provides a method of forming an integrated semiconductor device, and the device so formed. An active surface of at least two semiconductor devices, such as semiconductor chips, are temporarily mounted onto an alignment substrate. A support substrate is affixed to a back surface of the devices using a conformable bonding material, wherein the bonding material accommodates devices having different dimensions. The alignment substrate is then removed leaving the devices wherein the active surface of the devices are co-planar.

Abstract translation: 本发明提供一种形成集成半导体器件的方法以及如此形成的器件。 至少两个半导体器件（例如半导体芯片）的有源表面临时安装在对准衬底上。 支撑基板使用适形接合材料固定到装置的后表面，其中粘合材料容纳具有不同尺寸的装置。 然后去除对准衬底，留下其中器件的有源表面是共面的器件。

公开(公告)号：US06727118B2

公开(公告)日：2004-04-27

申请号：US10462273

申请日：2003-06-16

Applicant: Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

Inventor： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC: H01L2144

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

Abstract translation: 片上芯片模块及相关的形成方法。 第一和第二半导体芯片被耦合在一起。 第一芯片包括分别在第一芯片的第一和第二侧上的第一布线层和第一导电基板。 电源电压VDD适于电耦合到第一芯片的第二侧。 第二芯片包括分别在第二芯片的第一和第二侧上的第二布线层和第二导电基板。 接地电压GND适于电耦合到第二芯片的第二侧。 第一芯片的第一侧电耦合到第二芯片的第一侧。 电源电压VDD和接地电压GND适于为第一和第二芯片提供电力。

公开(公告)号：US06627477B1

公开(公告)日：2003-09-30

申请号：US09657232

申请日：2000-09-07

Applicant: Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

Inventor： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L2221/68363 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075

Abstract: The present invention provides a method of forming an integrated semiconductor device, and the device so formed. An active surface of at least two semiconductor devices, such as semiconductor chips, are temporarily mounted onto an alignment substrate. A support substrate is affixed to a back surface of the devices using a conformable bonding material, wherein the bonding material accommodates devices having different dimensions. The alignment substrate is then removed leaving the devices wherein the active surface of the devices are co-planar.

Abstract translation: 本发明提供一种形成集成半导体器件的方法以及如此形成的器件。 至少两个半导体器件（例如半导体芯片）的有源表面临时安装在对准衬底上。 支撑基板使用适形接合材料固定到装置的后表面，其中粘合材料容纳具有不同尺寸的装置。 然后去除对准衬底，留下其中器件的有源表面是共面的器件。