公开(公告)号：US07820521B2

公开(公告)日：2010-10-26

申请号：US12335605

申请日：2008-12-16

申请人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/76

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US20090120679A1

公开(公告)日：2009-05-14

申请号：US12335605

申请日：2008-12-16

申请人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01R12/22 ,  H01L21/768 ,  H05K3/42

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US07488680B2

公开(公告)日：2009-02-10

申请号：US11214602

申请日：2005-08-30

申请人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/4763

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US08440544B2

公开(公告)日：2013-05-14

申请号：US12899127

申请日：2010-10-06

申请人： Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/301

CPC分类号： H01L29/06 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2924/00011 ,  H01L2224/80001

摘要： CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.

摘要翻译： 具有替代衬底的CMOS结构和制造方法在本文中公开。 该方法包括在临时衬底上形成器件。 该方法还包括移除临时衬底。 所述方法还包括用固定结构将永久电绝缘衬底粘合到所述器件上。

公开(公告)号：US08263497B2

公开(公告)日：2012-09-11

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和终止于背面的多个盲电通路的组件和处理器晶片。 一个步骤包括将盲电通孔暴露在背面的各种高度上。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 并向后侧施加第二化学机械抛光工艺。

公开(公告)号：US20110037161A1

公开(公告)日：2011-02-17

申请号：US12540510

申请日：2009-08-13

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/488 ,  H01L21/78 ,  H01L21/50

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US08564113B2

公开(公告)日：2013-10-22

申请号：US13444193

申请日：2012-04-11

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US08242591B2

公开(公告)日：2012-08-14

申请号：US12540510

申请日：2009-08-13

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US20100261335A1

公开(公告)日：2010-10-14

申请号：US12423254

申请日：2009-04-14

申请人： Paul S. Andry ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/78

CPC分类号： H01L21/78

摘要： A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches.

摘要翻译： 一种方法包括接收具有前侧和后侧的至少一个晶片，其中前侧在其上具有多个集成电路芯片。 晶片的背面变薄，从晶片的背面去除材料图案以形成多个切割沟槽。 每个切割槽位于对应于多个芯片中的每一个的边缘的晶片正面的位置。 切割槽填充有填充材料，并且切割支撑件附接到晶片的前侧。 从切割槽移除填充材料，并且将力施加到切割支撑件，以将晶片上的多个芯片中的每一个沿着切割沟槽彼此分离。

公开(公告)号：US20100178766A1

公开(公告)日：2010-07-15

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side, to open the dielectric only adjacent the conductive cores of the vias.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和处理器晶片的组件。 主晶片具有在背面上方终止的多个盲电通路。 盲电通孔具有导电芯，其周围绝缘体邻近芯的侧面和端部区域。 处理器晶片固定到主晶片的主体的前侧。 另外的步骤包括在背面暴露盲电通孔。 盲孔通过背面暴露于各种高度。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 以及向后侧施加第二化学机械抛光工艺，以仅在通孔的导电芯附近打开电介质。