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    PRINTED CIRCUIT BOARD
    103.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20120051003A1

    公开(公告)日：2012-03-01

    申请号：US12953496

    申请日：2010-11-24

    Applicant: HUNG-YI CHIEN

    Inventor： HUNG-YI CHIEN

    IPC: H05K7/00

    CPC classification number: H05K1/0259 ,  H05K1/0231 ,  H05K2201/0738

    Abstract: A printed circuit board (PCB) includes an electronic element, a signal line, an input/output (I/O) interface, and a varistor. The I/O interface is connected to the electronic element through the signal line. The varistor includes a first terminal connected to the I/O interface, and a grounded second terminal. The varistor is close to the I/O interface, to eliminate static electricity flowing into the PCB from the I/O interface.

    Abstract translation: 印刷电路板（PCB）包括电子元件，信号线，输入/输出（I / O）接口和变阻器。 I / O接口通过信号线连接到电子元件。 变阻器包括连接到I / O接口的第一端子和接地的第二端子。 压敏电阻靠近I / O接口，以消除从I / O接口流入PCB的静电。

    In package ESD protections of IC using a thin film polymer
    107.
    发明授权
    In package ESD protections of IC using a thin film polymer 有权
    使用薄膜聚合物封装ESD保护IC

    公开(公告)号：US07872841B2

    公开(公告)日：2011-01-18

    申请号：US12049726

    申请日：2008-03-17

    Applicant: Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

    Inventor： Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

    IPC: H02H9/00

    CPC classification number: H01L23/62 ,  H01L23/60 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/15311 ,  H05K1/0259 ,  H05K2201/0738 ,  Y10T29/49105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

    Abstract translation: 一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛件（240） 。 两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。 一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。 类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。 轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

    Direct application voltage variable material
    108.
    发明授权
    Direct application voltage variable material 有权
    直接施加电压可变材料

    公开(公告)号：US07843308B2

    公开(公告)日：2010-11-30

    申请号：US11679064

    申请日：2007-02-26

    Applicant: Timothy Pachla ,  Edwin James Harris ,  Tushar Vyas

    Inventor： Timothy Pachla ,  Edwin James Harris ,  Tushar Vyas

    IPC: H01C7/10

    CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

    Abstract: A first voltage variable material (“VVM”) includes an insulative binder, first conductive particles with a core and a shell held in the insulating binder and second conductive particles without a shell held in the insulating binder; a second VVM includes an insulating binder, first conductive particles with a core and a shell held in the insulating binder, second conductive particles without a shell held in the insulating binder, and semiconductive particles with a core and a shell held in the insulating binder; a third VVM includes only first conductive particles with a core and a shell held in the insulating binder.

    Abstract translation: 第一电压可变材料（“VVM”）包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒和没有保持在绝缘粘合剂中的壳的第二导电颗粒; 第二VVM包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒，没有保持在绝缘粘合剂中的壳的第二导电颗粒和保持在绝缘粘合剂中的芯和壳的半导体颗粒; 第三VVM仅包括具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒。

    SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES
    109.
    发明申请
    SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES 审中-公开
    在基板设备的设计或仿真中包括保护电压可切换介质材料的系统和方法

    公开(公告)号：US20100281454A1

    公开(公告)日：2010-11-04

    申请号：US12834296

    申请日：2010-07-12

    Applicant: Lex Kosowsky ,  Robert Fleming

    Inventor： Lex Kosowsky ,  Robert Fleming

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5068 ,  H05K1/0254 ,  H05K1/0259 ,  H05K1/0293 ,  H05K1/0373 ,  H05K3/0005 ,  H05K2201/0738 ,  H05K2203/105

    Abstract: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device. The layer of VSD material may be positioned to protect one or more components of the substrate from the transient electrical condition.

    Abstract translation: 通过识别用于处理衬底装置上的瞬态电事件的一个或多个标准来设计衬底装置。 该一个或多个标准可以至少部分地基于从设计者提供的输入。 根据一个或多个标准，可以确定一个或多个特性，用于将VSD材料整合为衬底装置的至少一部分内或之上的层。 可以将VSD材料层定位成保护衬底的一个或多个部件免受瞬态电气条件的影响。

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