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    Response to tamper detection in a memory device
    112.
    发明授权
    Response to tamper detection in a memory device 有权
    对存储设备中的篡改检测的响应

    公开(公告)号：US09218509B2

    公开(公告)日：2015-12-22

    申请号：US14175063

    申请日：2014-02-07

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G06F21/78 ,  G06F21/86 ,  G11C7/24 ,  G11C11/16

    CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

    Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

    Abstract translation: 响应于篡改尝试指示，存储器设备选择性地禁用一个或多个存储器操作。 禁用可以通过不同的技术实现，包括改变与执行存储器操作相关联的偏置电压，选通执行存储器操作所需的电流，以及将所需电流限制在低于操作所需阈值幅度的幅度。 禁用内存操作后，可以生成模拟电流。 模拟电流旨在模拟在不被禁用时在存储器操作期间通常消耗的电流，从而导致用户认为即使正在尝试的存储器操作实际上不被执行，设备也继续正常地操作。

    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
    113.
    发明申请
    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE 审中-公开
    在记忆体设备中的篡改检测和响应

    公开(公告)号：US20150356322A1

    公开(公告)日：2015-12-10

    申请号：US14832495

    申请日：2015-08-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G06F21/79 ,  G06F21/60 ,  G11C11/16

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作，产生模拟电流以仿真在正常操作期间预期的电流，以及擦除存储在存储器件上的数据。

    METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE
    114.
    发明申请
    METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE 有权
    读取和写入具有错误校正代码的旋转扭矩随机存取存储器的方法

    公开(公告)号：US20150355967A1

    公开(公告)日：2015-12-10

    申请号：US14737558

    申请日：2015-06-12

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft

    IPC: G06F11/10 ,  G11C11/16

    CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1048 ,  G11C11/1673 ,  G11C11/1675 ,  H03M13/2906

    Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

    Abstract translation: 一种方法包括使用用于纠错的纠错码（ECC）和将反相或非反相数据存储在数据存储锁存器中来自动读取自旋扭矩磁随机存取存储器的位。 当随后的写入操作改变数据存储锁存器的状态时，启动奇偶校验计算和多数位的检测。 写入数据的多数位检测和潜在反转使写入电流脉冲的数量最小化。 在指定时间内或原始写入操作开始之前接收到的后续写入操作将导致多数检测操作中止。

    Systems and methods for dual standby modes in memory
    119.
    发明授权
    Systems and methods for dual standby modes in memory 有权

    公开(公告)号：US12020769B2

    公开(公告)日：2024-06-25

    申请号：US18189590

    申请日：2023-03-24

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam

    IPC: G11C7/10 ,  G11C5/14

    CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

    Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

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