公开(公告)号：US09698101B2

公开(公告)日：2017-07-04

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US09685522B1

公开(公告)日：2017-06-20

申请号：US15093952

申请日：2016-04-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42392 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/775

Abstract: Methods for forming uniform WF metal layers in gate areas of NS structures in a NS FET and the resulting devices are disclosed. Embodiments include providing NS structures, parallel to and spaced from each other, in a substrate; conformally forming gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure; forming a barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by PVD or PECVD; annealing the NS structures including the gate dielectric and metal layers; removing the barrier and metal layers from all surfaces; and forming a WF metal layer on all surfaces in the gate area of each NS structure.

公开(公告)号：US20170170118A1

公开(公告)日：2017-06-15

申请号：US15251804

申请日：2016-08-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

公开(公告)号：US20170141198A1

公开(公告)日：2017-05-18

申请号：US15283951

申请日：2016-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/417 ,  H01L29/16 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US20170125578A1

公开(公告)日：2017-05-04

申请号：US15298648

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US20170125414A1

公开(公告)日：2017-05-04

申请号：US15276060

申请日：2016-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/08

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US20170125299A1

公开(公告)日：2017-05-04

申请号：US15357287

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/517 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US09640535B2

公开(公告)日：2017-05-02

申请号：US15175540

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L23/485 ,  H01L21/8238 ,  H01L23/532

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76801 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region. The confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of the sidewall spacer and at least a portion of a sidewall surface of the etch stop layer, and a conductive contact element extends through the interlayer dielectric material and directly contacts an upper surface of the confined raised source/drain region.

公开(公告)号：US20170117274A1

公开(公告)日：2017-04-27

申请号：US14920354

申请日：2015-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L21/2018 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7853

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US09634110B2

公开(公告)日：2017-04-25

申请号：US15179393

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.