公开(公告)号：US10431648B2

公开(公告)日：2019-10-01

申请号：US16272736

申请日：2019-02-11

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/56 ,  H01L49/02 ,  H01L23/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/00 ,  H01L23/522 ,  H01L23/498

Abstract: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.

公开(公告)号：US10396041B2

公开(公告)日：2019-08-27

申请号：US15449993

申请日：2017-03-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC: H01L23/00 ,  H01L33/00 ,  H01L21/683 ,  H01L25/00 ,  H01L27/02 ,  H01L21/02 ,  H01L23/544

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

公开(公告)号：US20190237437A1

公开(公告)日：2019-08-01

申请号：US16378921

申请日：2019-04-09

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US20190221510A1

公开(公告)日：2019-07-18

申请号：US16361116

申请日：2019-03-21

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US20190088633A1

公开(公告)日：2019-03-21

申请号：US15919570

申请日：2018-03-13

Applicant: Invensas Corporation

Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L25/16 ,  H01L25/075 ,  H01L33/62 ,  H01L33/32 ,  H01L33/38 ,  H01L27/12 ,  H01L33/60 ,  H01L33/58 ,  H01L33/00 ,  H01L33/44

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

公开(公告)号：US10163833B2

公开(公告)日：2018-12-25

申请号：US15584961

申请日：2017-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen

IPC: H01L23/02 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/367 ,  H01L25/18 ,  B81B7/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  B81C1/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/34

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

公开(公告)号：US20180366436A1

公开(公告)日：2018-12-20

申请号：US15624494

申请日：2017-06-15

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/566 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/821 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/14

Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

公开(公告)号：US09831302B2

公开(公告)日：2017-11-28

申请号：US15360121

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US09754866B2

公开(公告)日：2017-09-05

申请号：US15248726

申请日：2016-08-26

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

公开(公告)号：US09691696B2

公开(公告)日：2017-06-27

申请号：US15005220

申请日：2016-01-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 620.3) connect the dies to the cavity's bottom wall (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.