公开(公告)号：US12125786B2

公开(公告)日：2024-10-22

申请号：US17819004

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B43/50 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20240315028A1

公开(公告)日：2024-09-19

申请号：US18604200

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Aaron S. Yip ,  Giovanni Mazzone ,  Matthew King

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.

公开(公告)号：US11961801B2

公开(公告)日：2024-04-16

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US11943938B2

公开(公告)日：2024-03-26

申请号：US17252357

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol

IPC: H10B99/00 ,  H01L21/768

CPC classification number: H10B99/00 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method for manufacturing a 3D vertical array of memory cells is disclosed. The method comprises:



forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each other;
forming holes through the stack of dielectric material layers, said holes exposing the substrate;
selectively removing the second material layers through said holes to form cavities between adjacent first dielectric material layers;
filling said cavities with a conductive material through said holes to form corresponding conductive material layers;
forming first memory cell access lines from said conductive material layers;
carrying out a conformal deposition of a chalcogenide material through said holes;
forming memory cell storage elements from said deposed chalcogenide material;
filling said holes with conductive material to form corresponding second memory cell access lines.

公开(公告)号：US11903196B2

公开(公告)日：2024-02-13

申请号：US17127971

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230397422A1

公开(公告)日：2023-12-07

申请号：US17884299

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard J. Hill ,  Paolo Tessariol

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

公开(公告)号：US20230337441A1

公开(公告)日：2023-10-19

申请号：US17720172

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Paolo Tessariol ,  Enrico Varesi ,  Lorenzo Fratin

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/249 ,  H01L45/06 ,  H01L45/16 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.

公开(公告)号：US11784058B2

公开(公告)日：2023-10-10

申请号：US17391345

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L21/311 ,  H01L23/522 ,  H01L23/64 ,  H01L21/62 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L21/31111 ,  H01L23/5223 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H10B43/27

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US11710724B2

公开(公告)日：2023-07-25

申请号：US17649022

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/768 ,  H01L23/481 ,  H01L23/4827 ,  H01L24/05 ,  H01L25/50

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US11700732B2

公开(公告)日：2023-07-11

申请号：US17146193

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H10B43/50 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.