公开(公告)号：US12051619B2

公开(公告)日：2024-07-30

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76804 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US12015055B2

公开(公告)日：2024-06-18

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11955553B2

公开(公告)日：2024-04-09

申请号：US18174045

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L21/24 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02694 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6681

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US11901455B2

公开(公告)日：2024-02-13

申请号：US17813888

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2221/1063

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20230352533A1

公开(公告)日：2023-11-02

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167 ,  H01L21/285

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11796922B2

公开(公告)日：2023-10-24

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Jyu-Horng Shieh ,  Liang-Yin Chen ,  Shu-Huei Suen ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yi-Nien Su ,  Yung-Sung Yen ,  Chia-Fong Chang ,  Ya-Wen Yeh ,  Yu-Tien Shen

IPC: G03F1/22 ,  G03F7/36 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70

CPC classification number: G03F7/70558 ,  G03F1/22 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/40 ,  G03F7/70033 ,  G03F7/70625 ,  H01L21/0274

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US11791204B2

公开(公告)日：2023-10-17

申请号：US17171210

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76825 ,  H01L21/76816 ,  H01L21/76822 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53242 ,  H01L23/53295

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

公开(公告)号：US11695042B2

公开(公告)日：2023-07-04

申请号：US17344049

申请日：2021-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Wen-Yen Chen ,  Li-Ting Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/165 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66553

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

公开(公告)号：US11652053B2

公开(公告)日：2023-05-16

申请号：US17171320

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US11610885B2

公开(公告)日：2023-03-21

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chia-Ling Chan ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.