公开(公告)号：US09337094B1

公开(公告)日：2016-05-10

申请号：US14589222

申请日：2015-01-05

申请人： International Business Machines Corporation

发明人： Balasubramanian Pranatharthiharan ,  Injo Ok ,  Charan V. V. S. Surisetty

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L29/41775 ,  H01L29/66848 ,  H01L29/812

摘要： A method of forming a contact is provided. The method may include forming a liner against a spacer around a gate; selectively removing an upper portion of the liner adjacent the spacer, forming a void; forming a spacer extension by filling the void with a spacer material; and forming a contact self-aligned to the spacer extension. A semiconductor structure is also disclosed. The structure may include: a gate; a spacer around the gate; a spacer extension extending laterally from an upper portion of the spacer; and a contact self-aligned to the spacer extension.

摘要翻译： 提供了形成接触的方法。 该方法可以包括围绕门的间隔件形成衬垫; 选择性地去除邻近间隔件的衬垫的上部，形成空隙; 通过用间隔物材料填充空隙来形成间隔物延伸部分; 并且形成与间隔物延伸部自对准的接触。 还公开了一种半导体结构。 该结构可以包括：门; 围绕门的间隔物; 间隔件延伸部，其从所述间隔件的上部横向延伸; 以及与间隔物延伸部自对准的接触。

公开(公告)号：US09240497B2

公开(公告)日：2016-01-19

申请号：US14167499

申请日：2014-01-29

申请人： GLOBALFOUNDRIES INC.

发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC分类号： H01L21/338 ,  H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

公开(公告)号：US20150357467A1

公开(公告)日：2015-12-10

申请号：US14300884

申请日：2014-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L29/41775 ,  H01L21/28052 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66848 ,  H01L29/66871 ,  H01L29/7835 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

摘要翻译： 公开了可调谐击穿电压RF MESFET和/或MOSFET及其制造方法。 该方法包括在下面的栅极电介质材料上形成第一条线和第二条线。 第二行具有调谐到击穿电压的宽度。 该方法还包括在第一和第二线路的侧壁上形成侧壁间隔物，使得第一和第二线路之间的空间被介电隔离物夹紧。 该方法还包括形成邻近第一线和第二线的外边缘的源极和漏极区域，以及移除至少第二线，以在第二线路的侧壁间隔物之间​​形成开口并暴露下面的栅极电介质材料。 该方法还包括在开口内的下面的栅极电介质材料上沉积材料层，以及形成与栅极结构和源极和漏极区域的接触。

公开(公告)号：US09202871B2

公开(公告)日：2015-12-01

申请号：US14275847

申请日：2014-05-12

申请人： Micron Technology, Inc.

发明人： Chandra Mouli

IPC分类号： H01L29/16 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66 ,  H01L29/808 ,  H01L29/812

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66848 ,  H01L29/66916 ,  H01L29/808 ,  H01L29/812 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.

摘要翻译： 提供了提供具有改进的操作特性的晶体管的装置。 在一个示例中，系统包括处理器和存储器设备。 处理器或存储器件的晶体管包括半导体衬底中的未掺杂或固有的沟道。 金属栅极直接设置在通道的顶部，半导体衬底的带隙和金属的功函形成肖特基势垒。

公开(公告)号：US09093548B2

公开(公告)日：2015-07-28

申请号：US13839213

申请日：2013-03-15

申请人： International Business Machines Corporation

发明人： Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L29/80 ,  H01L29/872 ,  H01L29/165

CPC分类号： H01L29/8086 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66431 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/802 ,  H01L29/808 ,  H01L29/8126 ,  H01L29/872

摘要： Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact.

摘要翻译： 提供了结点场效应晶体管，其包括位于第一导电类型的晶体半导体材料的表面上的栅极结。 栅极结可以从与第一导电类型相反的第二导电类型的掺杂氢化晶体半导体材料层部分中选择，第二导电类型的掺杂氢化非晶半导体材料层部分与第一导电类型相反， 导电型和肖特基接触。

公开(公告)号：US20140353667A1

公开(公告)日：2014-12-04

申请号：US13906738

申请日：2013-05-31

申请人： Infineon Technologies AG

发明人： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC分类号： H01L29/812 ,  H01L29/04 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

摘要： A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.

摘要翻译： 提供了具有主表面的半导体本体的场效应半导体器件。 半导体本体在基本上垂直于主表面的垂直横截面中包括第一导电类型的漂移层，邻接漂移层的第一导电类型的半导体台面，基本上延伸到主表面并具有两个侧面 壁，以及布置在半导体台面旁边的第二导电类型的两个第二半导体区域。 两个第二半导体区域中的每一个至少与漂移层形成pn结。 在台面的两个侧壁中的至少一个侧面上形成整流结。 此外，提供了一种异质结半导体器件的制造方法。

公开(公告)号：US08796808B2

公开(公告)日：2014-08-05

申请号：US12427256

申请日：2009-04-21

申请人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

发明人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

IPC分类号： H01L29/47

CPC分类号： H01L29/66848 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/66143 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/872

摘要： A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

摘要翻译： MOS PN结肖特基二极管器件包括具有第一导电类型的衬底，限定沟槽结构的场氧化物结构，形成在沟槽结构中的栅极结构以及与衬底中的栅极结构相邻的具有第二导电类型的掺杂区 。 在栅极结构的不同侧形成欧姆接触和肖特基接触。 制造这种二极管器件的方法包括几个离子注入步骤，以形成具有不同注入深度的多个掺杂子区域以构成掺杂区域。 形成的MOS P-N结肖特基二极管器件具有低正向压降，低反向漏电流，快速反向恢复时间和高反向电压容限。

公开(公告)号：US20140141585A1

公开(公告)日：2014-05-22

申请号：US14165120

申请日：2014-01-27

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shun-ichi NAKAMURA ,  Yasuyuki KAWADA

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/308

CPC分类号： H01L29/66666 ,  H01L21/02378 ,  H01L21/0337 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/308 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66522 ,  H01L29/66848 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.

摘要翻译： 提供了一种制造沟槽栅型MOSFET的方法，其中每个交叉沟槽形成为两级沟槽结构。 用掩模材料回填栅极沟槽，然后对掩模材料进行构图以形成用于形成每个交叉沟槽的掩模。 与栅极沟槽交叉的交叉沟槽设置成比栅极沟深。 在每个交叉沟槽10p的底部设置肖特基电极。 以这种方式，提供了沟槽栅型半导体器件及其制造方法，其中：即使使用宽带隙半导体作为主半导体衬底，也可以减小电池间距; 可以获得良好的欧姆接触; 并且防止了过量的电场被施加到每个沟槽的底部中的绝缘膜。

公开(公告)号：US20120146049A1

公开(公告)日：2012-06-14

申请号：US13400442

申请日：2012-02-20

申请人： Chandra Mouli

发明人： Chandra Mouli

IPC分类号： H01L29/47 ,  H01L21/338

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66848 ,  H01L29/66916 ,  H01L29/808 ,  H01L29/812 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

摘要翻译： 提供了提供具有改进的操作特性的JFET晶体管的器件和方法。 具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。 例如，一个或多个实施例包括具有掺杂碳化硅栅极的JFET，而其他实施例包括具有金属栅极的JFET。 一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

公开(公告)号：US08174054B2

公开(公告)日：2012-05-08

申请号：US12475162

申请日：2009-05-29

申请人： Robert Andrew Miller

发明人： Robert Andrew Miller

IPC分类号： H01L29/772

CPC分类号： H01L29/812 ,  H01L29/41758 ,  H01L29/66848 ,  H01L29/66863

摘要： A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer, and, a plurality of inactive gate channels, each inactive gate channel being defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer; the gate channels being arranged such that each active gate channel has a gate channel on each side; each active gate channel comprising a gate therein for controlling current flow in the electrically conducting channel layer.

摘要翻译： 一种场效应晶体管，包括其中包括导电沟道层的半导体衬底; 多个源极和漏极指在衬底的第一面上，每个手指通过栅极沟道与相邻的手指分离; 所述栅极沟道包括由源极指和漏极指限定的至少一个有源栅极通道，所述至少一个有源栅极通道布置在所述第一面上，使得所述电流可以经由所述导电沟道层自由地流过它们，并且，多个非活性栅极沟道 无源栅极通道由相同类型的两个手指或源极指和漏极指指定，源极指状物和漏极指状物布置在第一面上，使得电流不经由导电沟道层自由流动 ; 栅极通道被布置成使得每个有源栅极通道在每侧具有栅极通道; 每个有源栅极通道包括其中的栅极，用于控制导电沟道层中的电流。