公开(公告)号：US20140010022A1

公开(公告)日：2014-01-09

申请号：US14026359

申请日：2013-09-13

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：US20130343125A1

公开(公告)日：2013-12-26

申请号：US13799765

申请日：2013-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM ,  Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641

Abstract: Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused.

Abstract translation: 公开了在具有多个存储器状态的非易失性存储单元中进行操作的装置和方法。 其中一种方法是用于在非易失性存储单元中编程N位的方法，该非易失性存储单元被配置为存储多达N + 1位，其中N是大于零的整数。 编程方法包括在单元格中编程N位数据。 用于编程的方法还包括编程作为单元中N位数据的逻辑功能的附加位数据。 电池被配置为提供用于位存储的2N + 1阈值电压范围，并且根据逻辑功能：i）使用2N + 1个阈值电压范围的2N个阈值电压范围的第一组来存储N + 数据; 和ii）与第一组交替的2N个阈值电压范围的剩余的第二组未使用。

公开(公告)号：US20130326090A1

公开(公告)日：2013-12-05

申请号：US13903418

申请日：2013-05-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: G06F11/30 ,  G06F3/06

CPC classification number: G06F11/3065 ,  G06F3/0688 ,  G06F11/3037 ,  G06F11/3055 ,  G06F11/3082 ,  G06F13/1684 ,  G06F13/4256 ,  G11C7/1063

Abstract: A semiconductor device includes a bridging device having an external data interface, an external status interface, and a plurality of internal data interfaces. A plurality of memory devices are each connected to the bridging device via one of the internal data interfaces. Each of the memory devices has a ready/busy output connected to an input of the bridging device. The bridging device is configured to output a current state of each ready/busy output in a packetized format on the external status interface in response to a status request command received on the external status interface; and read information from a status register of a selected memory device over one of the internal data interfaces and provide the information on the external data interface in response to a status read command received on the external data interface. A method of operating a semiconductor device is also disclosed.

Abstract translation: 半导体器件包括具有外部数据接口，外部状态接口和多个内部数据接口的桥接器件。 多个存储器件各自经由内部数据接口之一连接到桥接器件。 每个存储器件具有连接到桥接器件的输入的就绪/忙碌输出。 桥接装置被配置为响应于在外部状态接口上接收的状态请求命令，在外部状态接口上以分组格式输出每个就绪/忙碌输出的当前状态; 并通过一个内部数据接口从所选择的存储器设备的状态寄存器读取信息，并根据在外部数据接口上接收到的状态读取命令提供有关外部数据接口的信息。 还公开了一种操作半导体器件的方法。

公开(公告)号：US08599984B2

公开(公告)日：2013-12-03

申请号：US13850500

申请日：2013-03-26

Applicant: MOSAID Technologies Incorporated

Inventor： Peter Vlasenko ,  Dieter Haerle

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract translation: 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

公开(公告)号：US20130318287A1

公开(公告)日：2013-11-28

申请号：US13955809

申请日：2013-07-31

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hong Beom PYEON ,  Hunsam JUNG ,  Peter B. GILLINGHAM

IPC: G06F1/08 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F1/08 ,  G06F3/0676 ,  G06F12/0246 ,  G06F13/1689 ,  G11C7/04

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。 系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置 复合存储器件。 响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

公开(公告)号：US20130275799A1

公开(公告)日：2013-10-17

申请号：US13796677

申请日：2013-03-12

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： George B. Raad

IPC: G06F1/04

CPC classification number: G06F1/3237 ,  G06F1/04 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G11C7/20 ,  G11C7/22 ,  G11C7/225 ,  G11C2207/2227 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

Abstract translation: 本发明包括用于选择性地关断内部时钟驱动器以减少工作电流的电路，系统和方法。 本发明可以用于通过减少存储器件中的工作电流来降低功耗。 通过关闭在选定的时间段内提供时钟信号的内部时钟驱动器，可以减少工作电流。 根据本发明的时钟控制电路的一个实施例，如果在没有进行读或写脉冲串操作的时段期间检测到无操作命令，则禁止内部时钟。 还公开了包括时钟控制电路及其功能的方法，存储器件和计算机系统。

公开(公告)号：US20130250695A1

公开(公告)日：2013-09-26

申请号：US13895591

申请日：2013-05-16

Applicant: Mosaid Technologies Incorporated

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/02

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US20130243137A1

公开(公告)日：2013-09-19

申请号：US13887937

申请日：2013-05-06

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hong Beom PYEON

IPC: H04L7/00

CPC classification number: G06F1/10 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H04L7/0008 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

公开(公告)号：US20130235659A1

公开(公告)日：2013-09-12

申请号：US13871487

申请日：2013-04-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Graham ALLAN

IPC: G11C16/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US20130170298A1

公开(公告)日：2013-07-04

申请号：US13776757

申请日：2013-02-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

IPC: G11C16/10

CPC classification number: G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。