公开(公告)号：US12020991B2

公开(公告)日：2024-06-25

申请号：US17412967

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hao Hou ,  Che-Hao Chang ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28185 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L21/823821

Abstract: A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.

公开(公告)号：US20240153952A1

公开(公告)日：2024-05-09

申请号：US18404606

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US20240113164A1

公开(公告)日：2024-04-04

申请号：US18151792

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Chia Su ,  Li-Fong Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

公开(公告)号：US20240079265A1

公开(公告)日：2024-03-07

申请号：US18151901

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/66439 ,  H01L29/66545

Abstract: A method includes depositing a first material on a sidewall surface of a recess in a substrate, wherein the first material is a conductive material; after depositing the first material, depositing a second material on a bottom surface of the recess using a plasma-assisted deposition process; and after depositing the second material, removing the first material.

公开(公告)号：US11915937B2

公开(公告)日：2024-02-27

申请号：US17378017

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/66553

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

公开(公告)号：US11908695B2

公开(公告)日：2024-02-20

申请号：US17377839

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Tsung-Ju Chen ,  Ta-Hsiang Kung ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L21/28141 ,  H01L21/0234 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

公开(公告)号：US11903221B2

公开(公告)日：2024-02-13

申请号：US17156320

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

公开(公告)号：US20240021706A1

公开(公告)日：2024-01-18

申请号：US18366460

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/0665 ,  H01L21/0228 ,  H01L29/42392

Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US11862508B2

公开(公告)日：2024-01-02

申请号：US17147798

申请日：2021-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chih-Tang Peng ,  Chi On Chui

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/76224 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111

Abstract: A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure.

公开(公告)号：US11854868B2

公开(公告)日：2023-12-26

申请号：US17329068

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76804 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/5283

Abstract: Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.