公开(公告)号：US09741615B1

公开(公告)日：2017-08-22

申请号：US15242951

申请日：2016-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53209 ,  H01L27/0886 ,  H01L28/00 ,  H01L29/785

Abstract: Structures for contacting a fin-type field-effect transistor (FinFET) and associated methods. First and second gate structures are formed. The second gate structure is separated from the first gate structure by a space that crosses over a top surface of a fin. At least one layer is formed in the space, and a hardmask layer is formed on the at least one layer. An opening is formed in the hardmask layer at a location that is above the top surface of the fin and that is between the first gate structure and the second gate structure. The at least one layer is etched at the location of the opening to form a contact hole extending through the at least one layer to the top surface of the fin. A contact, which is formed in the contact hole, is coupled with the top surface of the fin.

公开(公告)号：US09735152B2

公开(公告)日：2017-08-15

申请号：US14315602

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/6681

Abstract: A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication.

公开(公告)号：US09728615B2

公开(公告)日：2017-08-08

申请号：US14740872

申请日：2015-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods for forming the devices with fin contacts. One method includes, for instance: obtaining a wafer with at least one isolation region; forming at least one fin on the wafer; forming at least one sacrificial contact; forming at least one sacrificial gate; etching to recess the at least one fin; growing an epitaxial material over the at least one fin; performing replacement metal gate to the at least one sacrificial gate; depositing an interlayer dielectric layer; and forming at least one fin contact. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170162584A1

公开(公告)日：2017-06-08

申请号：US15289161

申请日：2016-10-08

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L27/11 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

公开(公告)号：US09646969B2

公开(公告)日：2017-05-09

申请号：US15208121

申请日：2016-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09576856B2

公开(公告)日：2017-02-21

申请号：US14524628

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/311 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract translation: 提出了用于促进纳米线结构的制造的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括，例如：提供基底; 在所述衬底上方提供第一材料层和第二材料层，所述第一材料层与所述第二材料层交错; 去除第一材料层和第二材料层的部分，去除形成多个纳米线堆叠，包括第一材料纳米线和第二材料纳米线; 从至少一个纳米线堆叠去除所述第一材料纳米线; 以及从至少一个其它纳米线堆叠去除所述第二材料纳米线，其中所述至少一个纳米线堆叠和至少一个其它纳米线堆叠分别包括p型纳米线堆叠和n型纳米线堆叠 。

公开(公告)号：US09496133B1

公开(公告)日：2016-11-15

申请号：US15161258

申请日：2016-05-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/11 ,  H01L21/3105

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin ends. A plasma nitridation process is performed to the set of exposed fin ends. The plasma nitridation process forms a set of nitride layer covered fin ends. Dielectric material is deposited over the FinFET structure. The dielectric is etched to reveal sidewalls of the fins and the set of nitride layer covered fin ends. The nitride layer prevents epitaxial growth at the set of spacer covered fin ends.

Abstract translation: 描述了一种用于防止半导体器件中的外延生长的方法。 该方法切割FinFET结构的翅片以形成一组暴露的翅片末端。 对一组暴露的翅片端进行等离子体氮化处理。 等离子体氮化处理形成一组覆盖鳍片的氮化物层。 电介质材料沉积在FinFET结构上。 电介质被蚀刻以显示翅片的侧壁和一组氮化物层覆盖的翅片端部。 氮化物层防止在间隔件覆盖的翅片端部处的外延生长。

公开(公告)号：US20160260743A1

公开(公告)日：2016-09-08

申请号：US15157786

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/12 ,  H01L21/311 ,  H01L21/321 ,  H01L29/78 ,  H01L21/84 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L27/1211 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

Abstract translation: 提供了用于形成具有用于改进的工艺窗口的自对准触点的半导体器件的装置和方法。 一种方法包括：例如：获得具有至少两个栅极的晶片，形成与所述至少两个栅极相邻的部分间隔件，以及在所述晶片上形成至少一个触点。 一个中间半导体器件包括例如：具有隔离区域的晶片，设置在隔离区域上的至少两个栅极，设置在隔离区域上的至少一个源极区域，设置在隔离区域上的至少一个漏极区域，以及设置在隔离区域上的至少一个漏极区域 位于所述至少两个门之间的至少一个触点，其中所述至少一个触点的第一部分接合所述至少一个源极区域或所述至少一个漏极区域，并且所述至少一个触点的第二部分在顶表面 的至少两个门。

公开(公告)号：US09337197B1

公开(公告)日：2016-05-10

申请号：US14525763

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/40 ,  H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US09324842B2

公开(公告)日：2016-04-26

申请号：US14135716

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chun-chen Yeh ,  Tenko Yamashita ,  Veeraraghavan Basker

IPC: H01L31/072 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L29/41791 ,  H01L29/785

Abstract: A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer.

Abstract translation: 公开了一种用于制造具有埋入局部互连的鳍片的方法，以及所得到的器件。 实施例包括在BOX层上形成硅翅片，在硅鳍片的一部分上形成垂直于硅鳍片的栅电极，在栅电极的每个相对侧上形成间隔物，在硅片上形成源极/漏极区域 在栅电极的相对侧，使BOX层凹陷，在栅电极的相对侧处切割硅鳍和源极/漏极区，并在BOX层的凹陷部分上形成局部互连。