公开(公告)号：US20160254382A1

公开(公告)日：2016-09-01

申请号：US14633351

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Gerd Zschaetzsch

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成堆叠在衬底上的叠层。 堆叠包括硅锗层和硅层，其中硅锗层具有第一锗浓度。 堆叠被冷凝以在锗层中产生第二锗浓度，其中第二锗浓度大于第一锗浓度。 形成包括叠层的翅片，并且形成覆盖在翅片上的浇口。

公开(公告)号：US09431508B2

公开(公告)日：2016-08-30

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。

公开(公告)号：US09412848B1

公开(公告)日：2016-08-09

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US20160204129A1

公开(公告)日：2016-07-14

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H01L27/108 ,  H01L21/265 ,  H01L21/285 ,  H01L29/786 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：提供包括衬底的SOI晶片，在衬底上形成的掩埋氧化物（BOX）层和形成在BOX层上的半导体层，去除半导体 在所述晶片的第一区域中，以暴露所述BOX层，在所述第一区域中的暴露的BOX层上形成介电层，并在所述介电层上形成导电层。 此外，提供了包括形成在晶片上的电容器的半导体器件，其中电容器包括包括晶片的掺杂半导体衬底的第一电容器电极，包括晶片的超薄BOX层的电容器绝缘体和高k 形成在超薄BOX层上的电介质层，以及包含形成在高k电介质层上的导电层的第二电容器电极。

公开(公告)号：US09391176B2

公开(公告)日：2016-07-12

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L25/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/165 ,  H01L25/065 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US20160064123A1

公开(公告)日：2016-03-03

申请号：US14469012

申请日：2014-08-26

Applicant: Globalfoundries Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C1/16 ,  H01C17/075 ,  H01C7/18 ,  H01C7/00 ,  H01C7/02 ,  H01C7/04

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。

公开(公告)号：US09263270B2

公开(公告)日：2016-02-16

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/4763 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US20150287782A1

公开(公告)日：2015-10-08

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种方法包括提供半导体衬底，在半导体衬底上限定对应于纳米线的相对顶点的长度，去除半导体衬底的一部分以提供第一鳍结构和第二鳍结构，蚀刻第一腔 在所述第一侧附近沉积保护层，去除所述保护层的一部分以暴露所述半导体衬底的一部分，以及蚀刻所述第一和第二腔连通的所述暴露的半导体衬底处的第二腔。 第一鳍片结构和第二鳍片结构相邻，其中第一鳍片结构的长度对应于相对的顶点，并且具有第一侧面和第二侧面。

公开(公告)号：US20150287646A1

公开(公告)日：2015-10-08

申请号：US14244651

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括通过执行激光退火工艺来退火邻近p沟道栅叠层的半导体衬底中的卤注入区和延伸注入区。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US09123825B2

公开(公告)日：2015-09-01

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。