公开(公告)号：US10748602B2

公开(公告)日：2020-08-18

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel H. Morris ,  Kaushik Vaidyanathan ,  Niloy Mukherjee ,  Dmitri E. Nikonov ,  Ian Young ,  Tanay Karnik

IPC: G11C11/00 ,  G11C11/413 ,  G11C11/412 ,  G11C7/10 ,  G11C13/00 ,  G11C14/00 ,  G11C7/20

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20200242458A1

公开(公告)日：2020-07-30

申请号：US16258522

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Amrita Mathuriya ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) coupled to an analog in-memory artificial intelligence (AI) processor. A hybrid processor implementing the techniques according to an embodiment includes an AI processor configured to perform analog in-memory computations based on neural network (NN) weighting factors and input data provided by the CPU. The AI processor includes one or more NN layers. The NN layers include digital access circuits to receive data and weighting factors and to provide computational results. The NN layers also include memory circuits to store data and weights, and further include bit line processors and cross bit line processors to perform analog dot product computations between columns of the data memory circuits and the weight factor memory circuits. Some of the NN layers are configured as convolutional NN layers and others are configured as fully connected NN layers, according to some embodiments.

公开(公告)号：US20200152781A1

公开(公告)日：2020-05-14

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US20200083284A1

公开(公告)日：2020-03-12

申请号：US16128278

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Ian Young

IPC: H01L27/16 ,  H01L25/16 ,  H01L35/34 ,  H01L23/367 ,  H01L23/373 ,  H01L35/22 ,  H01L35/30 ,  H01L35/32

Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.

公开(公告)号：US20190386661A1

公开(公告)日：2019-12-19

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H03K19/18 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US20190385655A1

公开(公告)日：2019-12-19

申请号：US16009107

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

公开(公告)号：US20190305216A1

公开(公告)日：2019-10-03

申请号：US15942231

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Ian Young ,  Kevin O'Brien ,  Gary Allen ,  Noriyuki Sato

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G11C11/16 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization; an interconnect adjacent to the magnetic junction, wherein the interconnect comprises an antiferromagnetic (AFM) material which is doped with a doping material (Pt, Ni, Co, or Cr) and a structure adjacent to the interconnect such that the magnetic junction and the structure are on opposite surfaces of the interconnect, wherein the structure comprises a magnet with a second magnetization substantially different from the first magnetization.

公开(公告)号：US20190304653A1

公开(公告)日：2019-10-03

申请号：US15942434

申请日：2018-03-31

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Charles Kuo ,  Mark Doczy ,  Kevin O'Brien

IPC: H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.

公开(公告)号：US10416217B2

公开(公告)日：2019-09-17

申请号：US14749324

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Chia-Ching Lin ,  Yih Wang ,  Ian A. Young

IPC: G01R31/12 ,  G01R29/26 ,  G11C11/16 ,  G11C29/50 ,  G01R31/28

Abstract: Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.

公开(公告)号：US10081887B2

公开(公告)日：2018-09-25

申请号：US13715012

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Shawna M. Liff ,  Brian S. Doyle ,  Vivek K. Singh

IPC: D03D1/00 ,  D04H13/00 ,  D02G3/44

CPC classification number: D03D1/0088 ,  D02G3/441 ,  D04H13/00 ,  D10B2401/18 ,  Y10T442/3049 ,  Y10T442/3057 ,  Y10T442/3976 ,  Y10T442/603 ,  Y10T442/696

Abstract: Flexible electronically functional fabrics are described that allow for the placement of electronic functionality in flexible substrates such as traditional fabrics. The fabrics can be made using flexible electronically functional fibers or a combination of electronically functional fibers and textile fibers. Electronic devices can be incorporated into the fabric to give it full computing capabilities.