公开(公告)号：US20180047750A1

公开(公告)日：2018-02-15

申请号：US15596135

申请日：2017-05-16

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3105

CPC classification number: H01L27/1203 ,  H01L21/2253 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/76283 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/082 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6625 ,  H01L29/735

Abstract: A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.

公开(公告)号：US09893207B1

公开(公告)日：2018-02-13

申请号：US15462340

申请日：2017-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/788 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7889 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/66825

Abstract: A memory including a common floating gate structure in simultaneous electrical communication with a first fin structure of a first conductivity type vertically orientated semiconductor device and a second fin structure of a second conductivity type vertically orientated semiconductor device. A back bias electrode is present between the first and second fin structures embedded in a dielectric material positioned in a central portion of the common floating gate structure. The back bias electrode is present overlying an isolation region that is separating a first region of the substrate including the first conductivity type vertically orientated semiconductor device from a second region of the substrate including the second conductivity type vertically orientated semiconductor device.

公开(公告)号：US09893151B2

公开(公告)日：2018-02-13

申请号：US15404301

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/15 ,  H01L29/165 ,  H01L29/06 ,  H01L23/367 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/3677 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/157 ,  H01L29/165 ,  H01L29/785 ,  H01L2029/7858

Abstract: A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si1-xGex and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.

公开(公告)号：US09865462B2

公开(公告)日：2018-01-09

申请号：US15431454

申请日：2017-02-13

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/32

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/32

Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.

公开(公告)号：US09859420B1

公开(公告)日：2018-01-02

申请号：US15240598

申请日：2016-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/08

CPC classification number: H01L29/7827 ,  H01L21/02546 ,  H01L21/32133 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66977

Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.

公开(公告)号：US09859371B2

公开(公告)日：2018-01-02

申请号：US15154606

申请日：2016-05-13

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/165 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/308 ,  H01L29/78 ,  H01L29/161 ,  H01L29/737 ,  H01L29/10

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

公开(公告)号：US09847259B2

公开(公告)日：2017-12-19

申请号：US14743561

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L29/165 ,  H01L29/08 ,  H01L21/308 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/033 ,  H01L21/768 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

公开(公告)号：US20170358607A1

公开(公告)日：2017-12-14

申请号：US15177941

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/84 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/8213 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for forming a hybrid semiconductor device includes growing a stack of layers on a semiconductor substrate. The stack of layers includes a bottom layer in contact with the substrate, a middle layer on the bottom layer and a top layer on the middle layer. First and second transistors are formed on the top layer. A protective dielectric is deposited over the first and second transistors. A trench is formed adjacent to the first transistors to expose the middle layer. The middle layer is removed from below the first transistors to form a cavity. A dielectric material is deposited in the cavity to provide a transistor on insulator structure for the first transistors and a bulk substrate structure for the second transistors.

公开(公告)号：US09837415B2

公开(公告)日：2017-12-05

申请号：US14750455

申请日：2015-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/66795 ,  H01L29/7849

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins.

公开(公告)号：US09812530B2

公开(公告)日：2017-11-07

申请号：US15068601

申请日：2016-03-13

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  John Bruley ,  Pouya Hashemi ,  Ali Khakifirooz ,  John A. Ott ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L21/18 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L29/161 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/785

Abstract: Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.