公开(公告)号：US06974733B2

公开(公告)日：2005-12-13

申请号：US10463080

申请日：2003-06-16

申请人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

发明人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

摘要： There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

摘要翻译： 公开了一种装置，包括应变基片，包括通道的衬底上的器件，其中应变衬底沿着基本上垂直于沟道中的电流方向的方向施加器件。

公开(公告)号：US20130307513A1

公开(公告)日：2013-11-21

申请号：US13976414

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  G05F3/02 ,  H01L29/66

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US07494862B2

公开(公告)日：2009-02-24

申请号：US11529963

申请日：2006-09-29

申请人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

发明人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

IPC分类号： H01L21/8238

CPC分类号： H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

摘要翻译： 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。

公开(公告)号：US20080157162A1

公开(公告)日：2008-07-03

申请号：US11646757

申请日：2006-12-27

申请人： Brian S. Doyle ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Brian S. Doyle ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7841 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/1203

摘要： An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.

摘要翻译： 描述了具有在体硅衬底中制造的浮体单元和逻辑器件的集成电路。 浮体电池具有通过氧化电池体的下部而与衬底电隔离而形成的电浮体。

公开(公告)号：US20070034972A1

公开(公告)日：2007-02-15

申请号：US11588066

申请日：2006-10-25

申请人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta

发明人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.

摘要翻译： 本发明是一种半导体器件，其包括碳纳米管体，其具有形成在基底上的顶表面和侧向相对的侧壁。 栅极电介质层形成在碳纳米管体的上表面和碳纳米管体的横向相对侧壁上。 栅极电极形成在碳纳米管主体的顶表面上的栅极电介质上并且与碳纳米管体的横向相对的侧壁上的栅电介质相邻。

公开(公告)号：US09240410B2

公开(公告)日：2016-01-19

申请号：US13976413

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20130279145A1

公开(公告)日：2013-10-24

申请号：US13976413

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

摘要翻译： III-N族纳米线设置在基板上。 纳米线的纵向长度被限定为第一组III-N材料的沟道区域，与沟道区域的第一端电耦合的源极区域和与沟道区域的第二端电耦合的漏极区域。 第一组III-N材料上的第二组III-N材料用作纳米线表面上的电荷诱导层和/或阻挡层。 栅极绝缘体和/或栅极导体在通道区域内的纳米线周围同轴地包裹。 排水和源极接触件可以类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US07473947B2

公开(公告)日：2009-01-06

申请号：US10194506

申请日：2002-07-12

申请人： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

发明人： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

摘要翻译： 本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。 本发明还涉及一种形成晶体管的方法以及结合晶体管的系统。

公开(公告)号：US20070238281A1

公开(公告)日：2007-10-11

申请号：US11391510

申请日：2006-03-28

申请人： Mantu Hudait ,  Mohamad Shaheen ,  Loren Chow ,  Peter Tolchinsky ,  Joel Fastenau ,  Dmitri Loubychev ,  Amy Liu ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Mantu Hudait ,  Mohamad Shaheen ,  Loren Chow ,  Peter Tolchinsky ,  Joel Fastenau ,  Dmitri Loubychev ,  Amy Liu ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/28

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02549

摘要： Lattice mismatch and polar to non-polar issues may lead to dislocations and other defects between silicon or germanium substrates and group III-V materials such as indium antimonide. The provision of lattice matching layers and buffer layers may enable these defects to be reduced.

摘要翻译： 晶格错配和极性到非极性问题可能导致硅或锗衬底和III-V族III族材料如铟锑离子之间的位错和其他缺陷。 提供晶格匹配层和缓冲层可以使得能够减少这些缺陷。

公开(公告)号：US20060228840A1

公开(公告)日：2006-10-12

申请号：US11297084

申请日：2005-12-07

申请人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

发明人： Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott Hareland

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.